Computer Fundamentals 简明教程

Hierarchy − Computers normally have L1, L2, and L3 caches are the several layers of cache memory. The L1 cache is the smallest and fastest cache, located closest to the CPU; L2 and L3 caches are larger and slower.

Cache Organization − Each block or line of cache memory contains a small bit of data copied from the main memory. The CPU accesses cache memory in fixed-size blocks, not bytes.

Cache Coherency − Cache coherency ensures cached data matches the main memory data. Cache coherence techniques update other cores' caches when one core writes to a memory location in a multi-core processor.

Cache Replacement Policies − A cache replacement policy decides which block to evict when the cache is full and a new block is needed. LRU, FIFO, and Random Replacement are common policies.

Cache Access − The CPU checks the cache before reading or writing data. When data is cached, the CPU can quickly retrieve it. If data is not in the cache (cache miss), the CPU must fetch it from the main memory, which may delay it.

Cache Hierarchy − Modern processors contain L1, L2, and L3 caches that grow in capacity and latency farther from the CPU cores. Parallel access is achieved by splitting the L1 cache into instruction and data caches.

Cache Management − Optimization of cache utilization maximizes hit rates and minimizes miss penalties. Prefetching, where the processor predicts memory accesses and loads data into the cache, improves cache performance. Cache memory buffers frequently access data between the CPU and main memory to speed up processing and increase system performance. Modern computer systems require effective management and structure for optimal performance.

Instruction Execution − Registers hold the instructions that the CPU is currently running. This includes the operation code (opcode) and associated operands with it.

Data Storage − Registers store CPU-processed data. This can provide memory addresses, intermediate values during arithmetic or logical operations, and other data needed by the instructions being executed.

Addressing − Memory addresses are used to store or retrieve data from memory locations in RAM or other parts of the computer’s memory hierarchy.

Program Counter (PC) − Stores the memory address of the next instruction to be fetched and executed.

Instruction Register (IR) − Holds the current instruction being executed by the CPU.

Memory Address Register (MAR) − Stores the memory address of data being read from or written to memory.

Memory Data Register (MDR) − Contains the actual data being read from or written to memory.

General-Purpose Registers (GPRs) − Used for general data storage and manipulation during program execution.

High Bandwidth − VRAM typically offers high-speed data transfer rates, enabling fast access to graphical data by the GPU.

Parallel Access − VRAM is designed to support parallel access, allowing multiple rendering tasks to access different portions of the memory simultaneously.

Specialized Architecture − VRAM often has a specialized architecture optimized for graphics processing tasks, including features such as multi-port access and wide memory buses.

Dedicated Graphics Memory − Unlike system RAM, which is shared among various system components, VRAM is dedicated solely to graphics processing, ensuring that the GPU has sufficient memory bandwidth and capacity for rendering graphics-intensive applications.

GDDR (Graphics Double Data Rate) VRAM − This is the most commonly used type of VRAM, it is majorly found in modern GPUs. GDDR5, GDDR5X, and GDDR6 are some of the variants that provide improvements in power efficiency and bandwidth over earlier generations.

HBM (High Bandwidth Memory) − HBM VRAM is a more recent technology that provides even greater bandwidth at lower power consumption than conventional GDDR VRAM. It accomplishes this by minimising the distance data must travel between memory cells by stacking memory chips vertically on a silicon interposer.