Computer Logical Organization 简明教程
Combinational Circuits
组合电路是一种电路，我们在电路中组合不同的门，例如编码器、译码器、多路复用器和解复用器。组合电路的一些特性如下 -
Combinational circuit is a circuit in which we combine the different gates in the circuit, for example encoder, decoder, multiplexer and demultiplexer. Some of the characteristics of combinational circuits are following −
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The output of combinational circuit at any instant of time, depends only on the levels present at input terminals.
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The combinational circuit do not use any memory. The previous state of input does not have any effect on the present state of the circuit.
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A combinational circuit can have an n number of inputs and m number of outputs.
Block diagram
我们接下来将详细阐述几个重要的组合电路。
We’re going to elaborate few important combinational circuits as follows.
Half Adder
半加器是一种有两个输入和两个输出的组合逻辑电路。半加器电路旨在将两个单比特二进制数 A 和 B 相加。它是加两个 single 位数字的基本构建模块。此电路有两个输出 carry 和 sum 。
Half adder is a combinational logic circuit with two inputs and two outputs. The half adder circuit is designed to add two single bit binary number A and B. It is the basic building block for addition of two single bit numbers. This circuit has two outputs carry and sum.
Full Adder
全加器旨在克服半加器电路的缺点。它可以将两个单比特数字 A 和 B 以及进位 c 相加。全加器是一个有三个输入和两个输出的组合电路。
Full adder is developed to overcome the drawback of Half Adder circuit. It can add two one-bit numbers A and B, and carry c. The full adder is a three input and two output combinational circuit.
N-Bit Parallel Adder
全加器只能将两个单数字二进制数连同进位输入一起相加。但在实际中，我们需要将比一个比特长得多的二进制数相加。要加两个 n 位二进制数，我们需要使用 n 位并行加法器。它使用了级联的多位全加器。上一位全加器的进位输出连接到下一位全加器的进位输入。
The Full Adder is capable of adding only two single digit binary number along with a carry input. But in practical we need to add binary numbers which are much longer than just one bit. To add two n-bit binary numbers we need to use the n-bit parallel adder. It uses a number of full adders in cascade. The carry output of the previous full adder is connected to carry input of the next full adder.
4 Bit Parallel Adder
在框图中，A0 和 B0 表示四位字 A 和 B 的最低有效位。因此，全加器-0 是最低级。因此，其 Cin 已被永久设为 0。其余连接与 n 位并行加法器的连接完全相同，如图所示。四位并行加法器是一种非常常见的逻辑电路。
In the block diagram, A0 and B0 represent the LSB of the four bit words A and B. Hence Full Adder-0 is the lowest stage. Hence its Cin has been permanently made 0. The rest of the connections are exactly same as those of n-bit parallel adder is shown in fig. The four bit parallel adder is a very common logic circuit.
N-Bit Parallel Subtractor
可以通过取要减去的数的 1 或 2 的补数来进行减法。例如，可以通过将 B 的 1 或 2 的补数加到 A 来执行减法 (A-B)。这意味着我们可以使用二进制加法器来执行二进制减法。
The subtraction can be carried out by taking the 1’s or 2’s complement of the number to be subtracted. For example we can perform the subtraction (A-B) by adding either 1’s or 2’s complement of B to A. That means we can use a binary adder to perform the binary subtraction.
4 Bit Parallel Subtractor
首先将要减去的数字 (B) 通过反相器传递以获得其 1 的补数。然后，四位加法器将 A 和 B 的 2 的补数相加以产生减法。S3 S2 S1 S0 表示二进制减法 (A-B) 的结果，进位输出 Cout 表示结果的极性。如果 A > B，则 Cout = 0，二进制形式 (A-B) 的结果则 Cout = 1，结果为 2 的补数形式。
The number to be subtracted (B) is first passed through inverters to obtain its 1’s complement. The 4-bit adder then adds A and 2’s complement of B to produce the subtraction. S3 S2 S1 S0 represents the result of binary subtraction (A-B) and carry output Cout represents the polarity of the result. If A > B then Cout = 0 and the result of binary form (A-B) then Cout = 1 and the result is in the 2’s complement form.
Half Subtractors
半减法器是一种有两个输入和两个输出（差值和借位）的组合电路。它产生输入处两个二进制比特之间的差值，并且还生成一个输出（借位）以指示是否借用了 1。在减法 (A-B) 中，A 称为被减数位，B 称为减数位。
Half subtractor is a combination circuit with two inputs and two outputs (difference and borrow). It produces the difference between the two binary bits at the input and also produces an output (Borrow) to indicate if a 1 has been borrowed. In the subtraction (A-B), A is called as Minuend bit and B is called as Subtrahend bit.
Full Subtractors
全减法器克服了半减法器的缺点。全减法器是具有三个输入 A、B、C 和两个输出 D 和 C' 的组合电路。A 是“被减数”、B 是“减数”、C 是前一阶段产生的“借位”，D 是差值输出，C' 是借位输出。
The disadvantage of a half subtractor is overcome by full subtractor. The full subtractor is a combinational circuit with three inputs A,B,C and two output D and C'. A is the 'minuend', B is 'subtrahend', C is the 'borrow' produced by the previous stage, D is the difference output and C' is the borrow output.
Multiplexers
多路复用器是一种特殊类型的组合电路。有 n 个数据输入、一个输出和 m 个选择输入，其中 2m = n。它是一种数字电路，可选择 n 个数据输入中的一个并将其路由到输出。n 个输入中之一的选择通过所选输入来完成。根据应用于所选输入的数字代码，从 n 个数据源中选择一个并将其传输到单个输出 Y。E 称为选通或使能输入，它对于级联非常有用。它通常是一个低电平有效端，这意味着在低电平时，它将执行所需的操作。
Multiplexer is a special type of combinational circuit. There are n-data inputs, one output and m select inputs with 2m = n. It is a digital circuit which selects one of the n data inputs and routes it to the output. The selection of one of the n inputs is done by the selected inputs. Depending on the digital code applied at the selected inputs, one out of n data sources is selected and transmitted to the single output Y. E is called the strobe or enable input which is useful for the cascading. It is generally an active low terminal that means it will perform the required operation when it is low.
Demultiplexers
解复用器执行多路复用器的反向操作，即它接收一个输入并将其分配到多个输出上。它只有一个输入、n 个输出、m 个选择输入。一次只能通过选择线选择一个输出线，并且输入传输到所选输出线。解复用器等效于单刀多位开关，如图所示。
A demultiplexer performs the reverse operation of a multiplexer i.e. it receives one input and distributes it over several outputs. It has only one input, n outputs, m select input. At a time only one output line is selected by the select lines and the input is transmitted to the selected output line. A de-multiplexer is equivalent to a single pole multiple way switch as shown in fig.
解复用器有多种变化。
Demultiplexers comes in multiple variations.
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1 : 2 demultiplexer
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1 : 4 demultiplexer
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1 : 16 demultiplexer
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1 : 32 demultiplexer
Decoder
译码器是一种组合电路。它具有 n 个输入和最多 m = 2n 个输出。译码器与没有任何数据输入的解复用器相同。它执行与编码器完全相反的操作。
A decoder is a combinational circuit. It has n input and to a maximum m = 2n outputs. Decoder is identical to a demultiplexer without any data input. It performs operations which are exactly opposite to those of an encoder.
2 to 4 Line Decoder
2 到 4 线译码器的框图如图所示。A 和 B 是两个输入，D 到 D 是四个输出。真值表解释了译码器的操作。它显示每个输出仅对特定的输入组合为 1。
The block diagram of 2 to 4 line decoder is shown in the fig. A and B are the two inputs where D through D are the four outputs. Truth table explains the operations of a decoder. It shows that each output is 1 for only a specific combination of inputs.
Encoder
编码器是一种组合电路，设计用于执行解码器的逆运算。编码器有 n 条输入线和 m 条输出线。编码器生成与数字输入数对应的 m 位二进制码。编码器接受 n 个输入数字字，并将其转换为 m 位另一个数字字。
Encoder is a combinational circuit which is designed to perform the inverse operation of the decoder. An encoder has n number of input lines and m number of output lines. An encoder produces an m bit binary code corresponding to the digital input number. The encoder accepts an n input digital word and converts it into an m bit another digital word.
Priority Encoder
这是一种特殊类型的编码器。优先考虑输入线。如果同时出现两个或多个输入线为 1，则将考虑具有最高优先级的输入线。有四个输入 D0、D1、D2、D3 和两个输出 Y0、Y1。在四个输入中，D3 具有最高优先级，而 D0 具有最低优先级。这意味着，如果 D3 = 1，则无论其他输入如何，Y1 Y1 = 11。类似地，如果 D3 = 0 且 D2 = 1，则无论其他输入如何，Y1 Y0 = 10。
This is a special type of encoder. Priority is given to the input lines. If two or more input line are 1 at the same time, then the input line with highest priority will be considered. There are four input D0, D1, D2, D3 and two output Y0, Y1. Out of the four input D3 has the highest priority and D0 has the lowest priority. That means if D3 = 1 then Y1 Y1 = 11 irrespective of the other inputs. Similarly if D3 = 0 and D2 = 1 then Y1 Y0 = 10 irrespective of the other inputs.
