Computer Logical Organization 简明教程

Digital Counters

计数器是一种顺序电路。用于计数脉冲的数字电路称为计数器。计数器是触发器的最广泛应用。它是一组带有时钟信号的触发器。计数器有两种类型。

Counter is a sequential circuit. A digital circuit which is used for a counting pulses is known counter. Counter is the widest application of flip-flops. It is a group of flip-flops with a clock signal applied. Counters are of two types.

  1. Asynchronous or ripple counters.

  2. Synchronous counters.

Asynchronous or ripple counters

图中所示为 2 位波纹上升计数器的逻辑图。正在使用触发器(T)翻转。但我们也可以使用 JK 触发器,将 J 和 K 永久连接到逻辑 1。外部时钟应用于触发器 A 的时钟输入,QA 输出应用于下一触发器(即 FF-B)的时钟输入。

The logic diagram of a 2-bit ripple up counter is shown in figure. The toggle (T) flip-flop are being used. But we can use the JK flip-flop also with J and K connected permanently to logic 1. External clock is applied to the clock input of flip-flop A and QA output is applied to the clock input of the next flip-flop i.e. FF-B.

Logical Diagram

ripple counter diagram

Operation

S.N.

Condition

Operation

1

Initially let both the FFs be in the reset state

QBQA = 00 initially

2

After 1st negative clock edge

As soon as the first negative clock edge is applied, FF-A will toggle and QA will be equal to 1. QA is connected to clock input of FF-B. Since QA has changed from 0 to 1, it is treated as the positive clock edge by FF-B. There is no change in QB because FF-B is a negative edge triggered FF. QBQA = 01 after the first clock pulse.

3

After 2nd negative clock edge

On the arrival of second negative clock edge, FF-A toggles again and QA = 0. The change in QA acts as a negative clock edge for FF-B. So it will also toggle, and QB will be 1. QBQA = 10 after the second clock pulse.

4

After 3rd negative clock edge

On the arrival of 3rd negative clock edge, FF-A toggles again and QA become 1 from 0. Since this is a positive going change, FF-B does not respond to it and remains inactive. So QB does not change and continues to be equal to 1. QBQA = 11 after the third clock pulse.

5

After 4th negative clock edge

On the arrival of 4th negative clock edge, FF-A toggles again and QA becomes 1 from 0. This negative change in QA acts as clock pulse for FF-B. Hence it toggles to change QB from 1 to 0. QBQA = 00 after the fourth clock pulse.

Truth Table

ripple counter truthtable

Synchronous counters

如果“时钟”脉冲同时应用于计数器中的所有触发器,则这样的计数器称为同步计数器。

If the "clock" pulses are applied to all the flip-flops in a counter simultaneously, then such a counter is called as synchronous counter.

2-bit Synchronous up counter

FF-A 的 JA 和 KA 输入与逻辑 1 绑在一起。因此,FF-A 将作为触发器翻转。JB 和 KB 输入连接到 QA。

The JA and KA inputs of FF-A are tied to logic 1. So FF-A will work as a toggle flip-flop. The JB and KB inputs are connected to QA.

Logical Diagram

synchronous counter diagram

Operation

S.N.

Condition

Operation

1

Initially let both the FFs be in the reset state

QBQA = 00 initially.

2

After 1st negative clock edge

As soon as the first negative clock edge is applied, FF-A will toggle and QA will change from 0 to 1. But at the instant of application of negative clock edge, QA , JB = KB = 0. Hence FF-B will not change its state. So QB will remain 0. QBQA = 01 after the first clock pulse.

3

After 2nd negative clock edge

On the arrival of second negative clock edge, FF-A toggles again and QA changes from 1 to 0. But at this instant QA was 1. So JB = KB= 1 and FF-B will toggle. Hence QB changes from 0 to 1. QBQA = 10 after the second clock pulse.

4

After 3rd negative clock edge

On application of the third falling clock edge, FF-A will toggle from 0 to 1 but there is no change of state for FF-B. QBQA = 11 after the third clock pulse.

5

After 4th negative clock edge

On application of the next clock pulse, QA will change from 1 to 0 as QB will also change from 1 to 0. QBQA = 00 after the fourth clock pulse.

Classification of counters

根据计数进行的方式,同步或异步计数器分类如下:

Depending on the way in which the counting progresses, the synchronous or asynchronous counters are classified as follows −

  1. Up counters

  2. Down counters

  3. Up/Down counters

UP/DOWN Counter

上升计数器和下降计数器结合在一起得到一个上升/下降计数器。还提供了模式控制 (M) 输入以选择上升或下降模式。必须设计并使用组合电路,放在每对触发器之间,以实现上升/下降操作。

Up counter and down counter is combined together to obtain an UP/DOWN counter. A mode control (M) input is also provided to select either up or down mode. A combinational circuit is required to be designed and used between each pair of flip-flop in order to achieve the up/down operation.

  1. Type of up/down counters

  2. UP/DOWN ripple counters

  3. UP/DOWN synchronous counter

UP/DOWN Ripple Counters

在 UP/DOWN 纹波计数器里,所有 FF 以切换模式运行。因此,要使用 T 触发器或 JK 触发器。MSB 触发器直接接收时钟。但每个其他 FF 的时钟都从前一个 FF 的 (Q = Q_bar) 输出获得。

In the UP/DOWN ripple counter all the FFs operate in the toggle mode. So either T flip-flops or JK flip-flops are to be used. The LSB flip-flop receives clock directly. But the clock to every other FF is obtained from (Q = Q bar) output of the previous FF.

  1. UP counting mode (M=0) − The Q output of the preceding FF is connected to the clock of the next stage if up counting is to be achieved. For this mode, the mode select input M is at logic 0 (M=0).

  2. DOWN counting mode (M=1) − If M = 1, then the Q bar output of the preceding FF is connected to the next FF. This will operate the counter in the counting mode.

Example

3 位二进制上升/下降纹波计数器。

3-bit binary up/down ripple counter.

  1. 3-bit − hence three FFs are required.

  2. UP/DOWN − So a mode control input is essential.

  3. For a ripple up counter, the Q output of preceding FF is connected to the clock input of the next one.

  4. For a ripple up counter, the Q output of preceding FF is connected to the clock input of the next one.

  5. For a ripple down counter, the Q bar output of preceding FF is connected to the clock input of the next one.

  6. Let the selection of Q and Q bar output of the preceding FF be controlled by the mode control input M such that, If M = 0, UP counting. So connect Q to CLK. If M = 1, DOWN counting. So connect Q bar to CLK.

Block Diagram

updown counter diagram

Truth Table

updown counter truthtable

Operation

S.N.

Condition

Operation

1

Case 1 − With M = 0 (Up counting mode)

If M = 0 and M bar = 1, then the AND gates 1 and 3 in fig. will be enabled whereas the AND gates 2 and 4 will be disabled. Hence QA gets connected to the clock input of FF-B and QB gets connected to the clock input of FF-C. These connections are same as those for the normal up counter. Thus with M = 0 the circuit work as an up counter.

2

Case 2: With M = 1 (Down counting mode)

If M = 1, then AND gates 2 and 4 in fig. are enabled whereas the AND gates 1 and 3 are disabled. Hence QA bar gets connected to the clock input of FF-B and QB bar gets connected to the clock input of FF-C. These connections will produce a down counter. Thus with M = 1 the circuit works as a down counter.

Modulus Counter (MOD-N Counter)

2 位纹波计数器称为 MOD-4 计数器,3 位纹波计数器称为 MOD-8 计数器。因此,一般来说,n 位纹波计数器称为模 N 计数器。其中,MOD 数 = 2^n。

The 2-bit ripple counter is called as MOD-4 counter and 3-bit ripple counter is called as MOD-8 counter. So in general, an n-bit ripple counter is called as modulo-N counter. Where, MOD number = 2n.

Type of modulus

  1. 2-bit up or down (MOD-4)

  2. 3-bit up or down (MOD-8)

  3. 4-bit up or down (MOD-16)

Application of counters

  1. Frequency counters

  2. Digital clock

  3. Time measurement

  4. A to D converter

  5. Frequency divider circuits

  6. Digital triangular wave generator.