Computer Logical Organization 简明教程
Sequential Circuits
组合电路不使用任何存储器。因此，输入的上一个状态不会对电路的当前状态产生任何影响。但顺序电路具有存储器，因此输出可以根据输入而变化。此类电路使用上一个输入、输出、时钟和存储器单元。
The combinational circuit does not use any memory. Hence the previous state of input does not have any effect on the present state of the circuit. But sequential circuit has memory so output can vary based on input. This type of circuits uses previous input, output, clock and a memory element.
Flip Flop
触发器是一种顺序电路，它通常对输入进行取样，并且仅在特定时间瞬间而不是持续不断地更改输出。触发器被称为边沿触发型，而不是像锁存器一样被称为电平触发型。
Flip flop is a sequential circuit which generally samples its inputs and changes its outputs only at particular instants of time and not continuously. Flip flop is said to be edge sensitive or edge triggered rather than being level triggered like latches.
S-R Flip Flop
本质上是使用 NAND 门的 S-R 锁存器，带有一个附加的 enable 输入。它还被称为电平触发 SR-FF。这种情况下，只有当使能输入 (E) 处于活动状态时，才会在输出中形成电路。简而言之，如果 E = 1，该电路将作为 S-R 锁存器工作，但如果 E = 0，输出不会发生变化。
It is basically S-R latch using NAND gates with an additional enable input. It is also called as level triggered SR-FF. For this, circuit in output will take place if and only if the enable input (E) is made active. In short this circuit will operate as an S-R latch if E = 1 but there is no change in the output if E = 0.
Operation
S.N. |
Condition |
Operation |
1 |
S = R = 0 : No change |
If S = R = 0 then output of NAND gates 3 and 4 are forced to become 1. Hence R' and S' both will be equal to 1. Since S' and R' are the input of the basic S-R latch using NAND gates, there will be no change in the state of outputs. |
2 |
*S = 0, R = 1, E = |
Since S = 0, output of NAND-3 i.e. R' = 1 and E = 1 the output of NAND-4 i.e. S' = 0. Hence Qn+1 = 0 and Qn+1 bar = 1. This is reset condition. |
3 |
*S = 1, R = 0, E = |
Output of NAND-3 i.e. R' = 0 and output of NAND-4 i.e. S' = 1. Hence output of S-R NAND latch is Qn+1 = 1 and Qn+1 bar = 0. This is the reset condition. |
4 |
*S = 1, R = 1, E = |
As S = 1, R = 1 and E = 1, the output of NAND gates 3 and 4 both are 0 i.e. S' = R' = 0. Hence the Race condition will occur in the basic NAND latch. |
Master Slave JK Flip Flop
主从 JK FF 是两个 S-R FF 的级联，从第二个的输出到第一个的输入有反馈。主触发器是正面电平触发器。但由于时钟线中有反相器，从触发器将对负电平做出响应。因此，当时钟 = 1（正电平）时，主触发器处于活动状态，从触发器处于非活动状态。而当时钟 = 0（低电平）时，从触发器处于活动状态，主触发器处于非活动状态。
Master slave JK FF is a cascade of two S-R FF with feedback from the output of second to input of first. Master is a positive level triggered. But due to the presence of the inverter in the clock line, the slave will respond to the negative level. Hence when the clock = 1 (positive level) the master is active and the slave is inactive. Whereas when clock = 0 (low level) the slave is active and master is inactive.
Operation
S.N. |
Condition |
Operation |
1 |
J = K = 0 (No change) |
When clock = 0, the slave becomes active and master is inactive. But since the S and R inputs have not changed, the slave outputs will also remain unchanged. Therefore outputs will not change if J = K =0. |
2 |
J = 0 and K = 1 (Reset) |
Clock = 1 − Master active, slave inactive. Therefore outputs of the master become Q1 = 0 and Q1 bar = 1. That means S = 0 and R =1. Clock = 0 − Slave active, master inactive. Therefore outputs of the slave become Q = 0 and Q bar = 1. Again clock = 1 − Master active, slave inactive. Therefore even with the changed outputs Q = 0 and Q bar = 1 fed back to master, its output will be Q1 = 0 and Q1 bar = 1. That means S = 0 and R = 1. Hence with clock = 0 and slave becoming active the outputs of slave will remain Q = 0 and Q bar = 1. Thus we get a stable output from the Master slave. |
3 |
J = 1 and K = 0 (Set) |
Clock = 1 − Master active, slave inactive. Therefore outputs of the master become Q1 = 1 and Q1 bar = 0. That means S = 1 and R =0. Clock = 0 − Slave active, master inactive. Therefore outputs of the slave become Q = 1 and Q bar = 0. Again clock = 1 − then it can be shown that the outputs of the slave are stabilized to Q = 1 and Q bar = 0. |
4 |
J = K = 1 (Toggle) |
Clock = 1 − Master active, slave inactive. Outputs of master will toggle. So S and R also will be inverted. Clock = 0 − Slave active, master inactive. Outputs of slave will toggle. These changed output are returned back to the master inputs. But since clock = 0, the master is still inactive. So it does not respond to these changed outputs. This avoids the multiple toggling which leads to the race around condition. The master slave flip flop will avoid the race around condition. |
Delay Flip Flop / D Flip Flop
延迟触发器或 D 触发器是由 NAND 反相器连接在 S 和 R 输入之间形成的简单门控 S-R 锁存器。它只有一个输入。输入数据在一段时间后出现在输出中。由于输入和输出之间存在此数据延迟，因此它被称为延迟触发器。由于 NAND 反相器，S 和 R 将互为补码。因此，S = R = 0 或 S = R = 1，这些输入条件永远不会出现。这个问题可以通过 S R = 00 和 SR = 1 条件来避免。
Delay Flip Flop or D Flip Flop is the simple gated S-R latch with a NAND inverter connected between S and R inputs. It has only one input. The input data is appearing at the output after some time. Due to this data delay between i/p and o/p, it is called delay flip flop. S and R will be the complements of each other due to NAND inverter. Hence S = R = 0 or S = R = 1, these input condition will never appear. This problem is avoid by SR = 00 and SR = 1 conditions.
Toggle Flip Flop / T Flip Flop
触发器切换器本质上是 J 和 K 端子始终连接在一起的 JK 触发器。它只有 T 所指示的输入，如符号图所示。正边缘触发 T 触发器的符号在框图中显示。
Toggle flip flop is basically a JK flip flop with J and K terminals permanently connected together. It has only input denoted by T as shown in the Symbol Diagram. The symbol for positive edge triggered T flip flop is shown in the Block Diagram.
