Digital-electronics 简明教程
CMOS Logic Gate in Digital Electronics
What is a Logic Gate?
在数字电路中， a logic gate 是数字电路或系统的一个基本元件，它执行特定的逻辑操作。逻辑门通常有一个或多个输入端和一个输出端。逻辑门的输出基于某种逻辑与输入端相关联。
In digital circuits, a logic gate is a fundamental element of the digital circuit or system, that performs a specific logical operation. A logic gates typically has one or more inputs and only one output. The output of the logic gate is related to the inputs based on a certain logic.
一些常用的逻辑门有：AND 门、OR 门、NOT 门、NAND 门和 NOR 门。
Some commonly used logic gates are: AND Gate, OR Gate, NOT Gate, NAND Gate, and NOR Gate.
What is CMOS Technology?
CMOS, Complementary Metal Oxide Semiconductor ，是一种用于制造集成电路 (IC) 的主要技术。这种技术广泛用于制造各种数字电子组件，如微处理器、传感器、逻辑门等。
CMOS, Complementary Metal Oxide Semiconductor, is a predominant technology used for manufacturing integrated circuits (ICs). This technology is widely used for manufacturing a variety of digital electronic components like microprocessors, sensors, logic gates, and more.
CMOS 技术采用 NMOS（N 型金属氧化物半导体）和 PMOS（P 型金属氧化物半导体）逻辑来实现不同类型的数字功能。
CMOS technology employs both NMOS (N-Channel Metal Oxide Semiconductor) and PMOS (P-Channel Metal Oxide Semiconductor) logic to implement different types of digital functions.
CMOS 技术因其快速的开关速度、低功耗、高电压范围、高噪声容限等关键优势而被广泛用于实现数字逻辑门。
CMOS technology is widely being used in realizing digital logic gates due to its key advantages, such as fast switching speed, low power consumption, high voltage range, high noise margins, etc.
Basic CMOS Logic Gates
现在，让我们详细讨论基本的 CMOS 逻辑门。
Let us now discuss the basic CMOS logic gates in detail.
CMOS OR Gate
OR 门是数字电子器件中的一个基本逻辑门。OR 门在其任何一个输入端为高时产生高电平或逻辑 1 输出，当其所有输入端都为低时产生低电平或逻辑 0 输出。
The OR gate is a basic logic gate in digital electronics. OR gates produce a high or logic 1 output when any of its inputs is high, and it produces a low or logic 0 output when all of its inputs are low.
一个双输入 OR 门的真值表如下所示。
The truth table of a two-input OR gate is given below.
Input |
Output |
A |
B |
Y = A + B |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
0 |
1 |
1 |
1 |
使用 CMOS 逻辑实现双输入 OR 门如下图所示。
The implementation of a two input OR gate in CMOS logic is shown in the following figure.
此处，我们把多个 CMOS 反相器组合在一起构成一个 CMOS OR 门。在电路图中，CMOS OR 门由一个 PMOS 晶体管和一个 NMOS 晶体管组成，它们通过电源电压 (V) 与输出端连接起来。
Here, we have combined multiple CMOS inverters together to build a CMOS OR gate. In the circuit diagram, the CMOS OR gate consists of a PMOS transistor and an NMOS transistor, which are joined in parallel fashion between the power supply voltage (V) and the output.
在上图中， when one or both inputs (A and B) are high (logic 1) 相应的 PMOS 和 NMOS 晶体管以这样的方式切换，使电流从输出端流向接地，导致输出端出现低电压（逻辑 0）。
In the above circuit, when one or both inputs (A and B) are high (logic 1), the corresponding PMOS and NMOS transistors switch in a way that the current flows from the output to ground, causes a low voltage (logic 0) at the output terminal.
When both inputs are low (logic 0) ，相应的 CMOS 晶体管以这样的方式切换，使输出端与电源电压连接，导致输出端出现高电压（逻辑 1）。
When both inputs are low (logic 0), the corresponding CMOS transistors switch in a way that the output is connected to the supply voltage, causing a high voltage (logic 1) at the output terminal.
CMOS AND Gate
AND 门是一种用在各种数字逻辑电路中的基本逻辑门。AND 门仅在其所有输入端都为高时产生高电平或逻辑 1 输出，当其任何一个输入端为低时产生低电平或逻辑 0 输出。
The AND gate is a basic logic gate used in a variety of digital logic circuits. AND gate produces a high or logic 1 output only when all of its inputs are high, it produces a low or logic 0 output when any of its inputs is low.
双输入 AND 门的真值表如下所示。
The truth table of the two-input AND gate is given below.
Input |
Output |
A |
B |
Y = AB |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
0 |
1 |
1 |
使用 CMOS 技术实现 AND 门如下图所示。
The implementation of AND gate using CMOS technology is shown in the following figure.
此处，为了实现 CMOS AND 门，我们把多个 CMOS 反相器连接在一起。在 CMOS AND 门电路中，PMOS 和 NMOS 晶体管用于构建它。这些晶体管分别串联在电源电压 (V) 和输出端 (Y) 之间，并联在输出端和接地之间。
Here, to implement the CMOS AND gate, we have connected multiple CMOS inverters together. In the CMOS AND gate circuit, PMOS and NMOS transistors are used to build it. These transistors are connected in series between supply voltage (V) and the output (Y), and in parallel between the output and ground respectively.
在上图所示的 CMOS 与门电路中，当两个输入端均为高电平（逻辑 1）时，CMOS 晶体管会以这样的方式进行切换，使输出端连接到电源电压 (V)，产生一个高电平（逻辑 1）的输出。
In the case of CMOS AND gate shown in the above figure, when both inputs are high (logic 1), the CMOS transistors switch in such a way that the output is connected to the power supply voltage (V), producing a high (logic 1) output.
当任何输入端为低电平时，电路中的 CMOS 晶体管会以这样的方式进行切换，使电流从电源流向接地，从而使输出端为低电平（逻辑 0）。
When any of its inputs is low, the CMOS transistors in the circuit switch such that the current flows from power supply to the ground, making output low (logic 0).
CMOS NOT Gate
非门也是数字电路中使用的一个基本逻辑门。非门具有一个输入端和一个输出端。当输入端为低电平或逻辑 0 时，非门的输出端为高电平或逻辑 1；当输入端为高电平或逻辑 1 时，其输出端为低电平或逻辑 0。
A NOT gate is also a basic logic gate used in digital logic circuits. The NOT has a single input and a single output. The output of the NOT gate is high or logic 1 when its input is low or logic 0, and its output is low or logic 0 when its input is high or logic 1.
在 CMOS 逻辑门中，CMOS 非门是最简单的 CMOS 逻辑门。它也被称为反相器。
In CMOS logic gates, the CMOS NOT gate is the simplest CMOS logic gate. It is also called CMOS Inverter Gate.
非门的真值表如下所示。
The truth table of the NOT gate is given below.
Input |
Output |
A |
Y = A' |
0 |
1 |
1 |
0 |
CMOS 技术中非门的实现如下图所示。
The implementation of a NOT gate in CMOS technology is shown in the following figure.
在此，输入端加到两个 CMOS 晶体管的栅极端，而输出端连接到它们的漏极端。
Here, the input is applied to the gate terminal of the two CMOS transistor, and the output is connected to their drain terminals.
当给输入端 Vi 加一个正电压脉冲（逻辑 1）时，CMOS 晶体管 Q1 处于关闭状态，CMOS 晶体管 Q2 处于导通状态。因此，输出电压将处于接地电压，即逻辑 0。
When a positive voltage pulse (logic 1) is applied to the input Vi, the CMOS transistor Q1 is off and the CMOS transistor Q2 is on. Therefore, the output voltage will be at ground voltage, i.e. logic 0.
当给输入端 Vi 加接地电压（逻辑 0）时，CMOS 晶体管 Q1 处于导通状态，CMOS 晶体管 Q2 处于关闭状态。因此，输出端将接通 +V，即逻辑 1。
When the ground voltage (logic 0) is applied to the input Vi, the CMOS transistor Q1 is on and the CMOS transistor Q2 is off. Thus, the output will be closed to +V, i.e. logic 1.