Digital-electronics 简明教程
Design Full Adder Using Half Adder
在数据处理中，对操作数的 addition 是计算机、计算器等不同电子设备执行的最基本操作之一。用来执行两个或更多数字（特别是二进制数字）相加的电子电路称为 adder. 。众所周知，逻辑电路使用二进制数字系统执行操作，因此加法器也被称为 binary adder. 。
In data processing, addition of operands is one of the most basic operations performed by different electronic devices like computers, calculators, etc. The electronic circuit that is designed to perform the addition of two or more numbers, more specifically binary numbers, is known as adder. As we know, the logic circuits use binary number system to perform the operations, hence the adder is also referred to as a binary adder.
Types of Adders
取决于加法器电路可以相加的二进制位数，加法器（或二进制加法器）有两种类型 −
Depending on the number of binary digits that the adder circuit can add, adders (or binary adders) are of two types −
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Half Adder
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Full Adder
在此，我们将讨论使用半加法器实现全加法器。但在那之前，让我们了解一下半加法器和全加法器的基础知识。
Here, we will discuss the implementation of full adder using half adder. But before that let’s have a look into the basics of half adder and full adder.
What is a Half Adder?
Half adder 是一种组合逻辑电路，用于对两个二进制位进行相加。半加法器提供输出并带有进位（如有）。通过连接一个异或门和一个与门，可以设计半加法器电路。它有两个输入端和两个输出端，用于和（S）和进位（©）。半加法器的框图和电路图如图 1 所示。
Half adder is a combinational logic circuit that is designed to add two binary digits. The half adder provides the output along with a carry (if any). The half adder circuit can be designed by connecting an XOR gate and one AND gate. It has two input terminals and two output terminals for sum (S) and carry ©. The block diagram and circuit diagram of a half adder are shown in Figure-1.
在半加法器中，异或门的输出是两个位的和，而与门的输出是进位位。然而，在半加法器电路中，一次相加中获得的进位不会转发到下一次相加中。
In the half adder, the output of the XOR gate is the sum of two bits and the output of the AND gate is the carry bit. However, in the half-adder circuit, the carry obtained in one addition will not be forwarded in the next addition.
半加法器的输出方程为，
The output equation of the half adder are,
\mathrm{和，\:S\:=\:A\:\oplus\:B}
\mathrm{Sum, \: S \: = \: A \: \oplus \: B}
\mathrm{进位，\:C\:=\:A\:\cdot\ B}
\mathrm{Carry, \: C \: = \: A \: \cdot \ B}
What is a Full Adder?
全加法器也是一种组合逻辑电路，可以对两个二进制位（位）和一个进位位进行相加，并产生一个和位和一个进位位作为输出。
Full adder is also a combinational logic circuit that can add two binary digits (bits) and a carry bit, and produces a sum bit and a carry bit as output.
换句话说，一个用于对三个二进制位进行相加并产生两个输出（和和进位）的组合电路称为全加法器。因此，全加法器电路对三个二进制位进行相加，其中两个是输入，一个是来自前一次相加的进位。全加法器的框图和电路图如图 2 所示。
In other words, a combinational circuit which is designed to add three binary digits and produces two outputs (sum and carry) is known as a full adder. Thus, a full adder circuit adds three binary digits, where two are the inputs and one is the carry forwarded from the previous addition. The block diagram and circuit diagram of the full adder are shown in Figure-2.
很明显，全加法器的逻辑电路由一个异或门、三个与门和一个或门组成，它们按照图 2 所示连接在一起。在此，A 和 B 是输入位，Cin 是来自前一次相加的进位，S 是和位，Cout 是输出进位位。
It is clear that the logic circuit of a full adder consists of one XOR gate, three AND gates and one OR gate, which are connected together as shown in Figure-2. Here, A and B are the input bits, Cin is the carry from previous addition, S is the sum bit, and Cout is the output carry bit.
全加法器的输出方程为，
The output equations of the full adder are,
\mathrm{和，\:S\:=\:A\:\oplus\:B\:\oplus\:C_{in}}
\mathrm{Sum, \: S \: = \: A \: \oplus \: B \: \oplus \: C_{in}}
\mathrm{进位，\:C_{out}\:=\:Ab\:+\:AC_{in}\:\+\:BC_{in}}
\mathrm{Carry, \: C_{out} \: = \: Ab \: + \: AC_{in} \: + \: BC_{in}}
现在，我们来讨论使用半加法器实现全加法器
Now, let us discuss the realization of the full adder using half adders
Implementation of Full Adder using Half Adder
使用两个半加法器的全加法器的逻辑图如图 3 所示
The logic diagram of the full adder using two half adders is shown in Figure-3 −
使用两个半加法器的全加法器的框图如图 4 所示
The block diagram of a full adder using two half adders is shown in Figure-4.
从使用半加法器的全加法器的逻辑图中可以清楚地看出，我们需要两个 XOR 门、两个 AND 门和一个 OR 门才能实现使用半加法器的全加法器电路
From the logic diagram of the full adder using half adders, it is clear that we require two XOR gates, two AND gates and one OR gate for the implementation of a full adder circuit using half-adders.
但是，使用半加法器实现全加法器有一个主要的缺点，那就是传播延迟增加。这意味着，输入位必须依次通过几个门，这会增加全加法器电路的总传播延迟
However, the implementation of full adder using half adder has a major disadvantage that is the increased propagation delay. That means, the input bits must propagate through several gates in succession that increases the total propagation delay of the full adder circuit.