Digital-electronics 简明教程

Digital Electronics - Decoders

What is a Decoder?

在数字电子设备中,组合逻辑电路以这样的方式将 N 位二进制输入代码转换到 M 个输出通道,即对于每种可能的输入组合,只对一个输出通道进行激活,称为 decoder

In digital electronics, a combinational logic circuit that converts an N-bit binary input code into M output channels in such a way that only one output channel is activated for each one of the possible combinations of inputs is known as a decoder.

换句话说,将 N 条输入线转换成最多 2N 条输出线的组合逻辑电路称为 decoder

In other words, a combinational logic circuit which converts N input lines into a maximum of 2N output lines is called a decoder.

因此,解码器是一个组合逻辑电路,能够识别或检测特定的代码。解码器执行的操作被称为解码。图 1 展示了一个解码器的通用框图。

Therefore, a decoder is a combination logic circuit that is capable of identifying or detecting a particular code. The operation that a decoder performs is referred to as decoding. A general block diagram of a decoder is shown in Figure-1.

block diagram decoder

在此,解码器有 N 条输入线和 M(2N)条输出线。在解码器中,每条 N 条输入线都可以是 0 或 1,因此可能的输入组合或代码的数量等于 2N。对于每种这些输入组合,只有 M 条输出线中的一条将处于活动状态,并且所有其他输出线都将保持非活动状态。

Here, the decoder has N input lines and M (2N) output lines. In a decoder, each of the N input lines can be a 0 or a 1, hence the number of possible input combinations or codes be equal to 2N. For each of these input combinations, only one of the M output lines will be active, and all other output lines will remain inactive.

Types of Decoders

当前有多种类型的解码器。但是,根据现有的输入线和输出线,可以将解码器分类为以下三种类型−

There are several types of decoder present. But, based on the input and output lines present, decoders may classified into the following three types −

  1. 2 to 4 Decoder

  2. 3 to 8 Decoder

  3. 4 to 16 Decoder

现在,让我们逐个详细讨论每种类型的解码器。

Now, let us discuss each type of decoder in detail one by one.

2 to 4 Decoder

2 到 4 解码器具有 2 条输入线和 4 条(22)输出线。图 2 显示了 2 到 4 解码器的功能框图。

The 2 to 4 decoder is one that has 2 input lines and 4 (22) output lines. The functional block diagram of the 2 to 4 decoder is shown in Figure-2.

2 to 4 decoder

当使用使能输入 E 启用此解码器时,它的四个输出之一对于每种输入组合都会处于活动状态。可以使用下面提供的真值表分析这个 2 线到 4 线解码器的操作。

When this decoder is enabled with the help of enable input E, then its one of the four outputs will be active for each combination of inputs. The operation of this 2-line to 4-line decoder can be analyzed with the help of its truth table which is given below.

Inputs

Outputs

E

A

B

Y3

Y2

Y1

Y0

0

X

X

0

0

0

0

1

0

0

0

0

0

1

1

0

1

0

0

1

0

1

1

0

0

1

0

0

1

1

1

1

0

0

0

我们可以使用此真值表得出每个输出的布尔表达式,如下所示:

Using this truth table, we can derive the Boolean expression for each output as follows −

Y0 := E ⋅ A̅ ⋅ B̅

\mathrm{Y_{0} \: = \: E \: \cdot \: \bar{A} \: \cdot \: \bar{B}}

Y1 := E ⋅ A̅ ⋅ B

\mathrm{Y_{1} \: = \: E \: \cdot \: \bar{A} \: \cdot \: B}

Y2 := E ⋅ A ⋅ B̅

\mathrm{Y_{2} \: = \: E \: \cdot \: A \: \cdot \: \bar{B}}

Y_3 = E ⋅ A ⋅ B

\mathrm{Y_{3} \: = \: E \: \cdot \: A \: \cdot \: B}

由于每个输出项都包含可以用 AND 门实现的输入变量的乘积。因此,2 到 4 解码器的逻辑电路图如图 3 所示。

As each output term contains products of input variables that can be implemented with the help of AND gates. Therefore, the logic circuit diagram of the 2 to 4 decoder is shown in Figure-3.

2 to 4 decoder circuit diagram

2 到 4 解码器的逻辑电路的操作如下所述 -

The operation of logic circuit of the 2 to 4 decoder is described as follows −

  1. When enable input (E) is inactive, i.e. set to 0, none of the AND gates will function.

  2. When enable input (E) is made active by setting it to 1, then the circuit works as explained below.

  3. When A = 0 and B = 0, the AND gate 1 becomes active and produces output Y0.

  4. When A = 0 and B = 1, the AND gate 2 becomes active and produces output Y1.

  5. When A = 1 and B = 0, the AND gate 3 becomes active and produces output Y2.

  6. When A = 1 and B = 1, the AND gate 4 becomes active and produces output Y3.

3 to 8 Decoder

3 到 8 解码器是具有 3 个输入线和 8 个 (23) 个输出线的解码器。3 到 8 解码器的功能框图如图 4 所示。

The 3 to 8 decoder is one that has 3 input lines and 8 (23) output lines. The functional block diagram of the 3 to 8 decoder is shown in Figure-4.

3 to 8 decoder

当该解码器在使能输入 E 的帮助下被使能后,对于每组输入,8 个输出线中有一个将激活。可以用其功能表(如下所示)来分析这个 3 线到 8 线解码器的操作。

When this decoder is enabled with the help of enable input E, then it’s one of the eight outputs will be active for each combination of inputs. The operation of this 3-line to 8-line decoder can be analyzed with the help of its function table which is given below.

Inputs

Outputs

E

A

B

C

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

0

X

X

X

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

1

1

0

0

1

0

0

0

0

0

0

1

0

1

0

1

0

0

0

0

0

0

1

0

0

1

0

1

1

0

0

0

0

1

0

0

0

1

1

0

0

0

0

0

1

0

0

0

0

1

1

0

1

0

0

1

0

0

0

0

0

1

1

1

0

0

1

0

0

0

0

0

0

1

1

1

1

1

0

0

0

0

0

0

0

使用此功能表,我们可以导出每个输出的布尔表达式如下 -

Using this function table, we can derive the Boolean expression for each output as follows −

\mathrm{Y_{0} \: = \: E \: \bar{A} \: \bar{B} \: \bar{C}}

\mathrm{Y_{1} \: = \: E \: \bar{A} \: \bar{B} \: C}

\mathrm{Y_{2} \: = \: E \: \bar{A} \: B \: \bar{C}}

\mathrm{Y_{3} \: = \: E \: \bar{A} \: B \: C}

\mathrm{Y_{4} \: = \: E \: A \: \bar{B} \: \bar{C}}

\mathrm{Y_{5} \: = \: E \: A \: \bar{B} \: C}

\mathrm{Y_{6} \: = \: E \: A \: B \: \bar{C}}

\mathrm{Y_{7} \: = \: E \: A \: B \: C}

正如我们所见,每个输出项都包含输入变量的乘积,因此它们可以用与门来实现。因此,3 到 8 解码器的逻辑电路图如图 5 所示。

As we can see, each output term contains products of input variables, hence they can be implemented with the help of AND gates. Therefore, the logic circuit diagram of the 3 to 8 decoder is shown in Figure-5.

3 to 8 decoder circuit diagram

3 到 8 解码器的逻辑电路操作如下所述 −

The operation of logic circuit of the 3 to 8 decoder is described as follows −

  1. When enable input (E) is inactive, i.e. set to 0, none of the AND gates will function.

  2. When enable input (E) is made active by setting it to 1, then the circuit works as described below.

  3. When A = 0, B = 0, and C = 0, the AND gate 1 becomes active and produces output Y0.

  4. When A = 0, B = 0, and C = 1, the AND gate 2 becomes active and produces output Y1.

  5. When A = 0, B = 1, and C = 0, the AND gate 3 becomes active and produces output Y2.

  6. When A = 0, B = 1, and C = 1, the AND gate 4 becomes active and produces output Y3.

  7. When A = 1, B = 0, and C = 0, the AND gate 5 becomes active and produces output Y4.

  8. When A = 1, B = 0, and C = 1, the AND gate 6 becomes active and produces output Y5.

  9. When A = 1, B = 1, and C = 0, the AND gate 7 becomes active and produces output Y6.

  10. When A = 1, B = 1, and C = 1, the AND gate 8 becomes active and produces output Y7.

4 to 16 Decoder

4 到 16 解码器是具有 4 个输入行和 16(214)个输出行的一种解码器。4 到 16 解码器的功能框图如图 6 所示。

The 4 to 16 decoder is the type of decoder which has 4 input lines and 16 (214) output lines. The functional block diagram of the 4 to 16 decoder is shown in Figure-6.

4 to 16 decoder

如果借助使能输入 E 启用此解码器,则对于输入的每个组合,它的 16 个输出之一将被激活。借助其功能表(如下所示),可以分析 4 行到 16 行解码器的操作。

When this decoder is enabled with the help of enable input E, it’s one of the sixteen outputs will be active for each combination of inputs. The operation of the 4-line to 16-line decoder can be analyzed with the help of its function table which is given below.

Inputs

Output

E

A

B

C

D

0

X

X

X

X

0

1

0

0

0

0

Y0

1

0

0

0

1

Y1

1

0

0

1

0

Y2

1

0

0

1

1

Y3

1

0

1

0

0

Y4

1

0

1

0

1

Y5

1

0

1

1

0

Y6

1

0

1

1

1

Y7

1

1

0

0

0

Y8

1

1

0

0

1

Y9

1

1

0

1

0

Y10

1

1

0

1

1

Y11

1

1

1

0

0

Y12

1

1

1

0

1

Y13

1

1

1

1

0

Y14

1

1

1

1

1

在此功能表中,我们可以直接为每个输出写入布尔表达式,如下所示 −

From this function table, we can directly write the Boolean expression for each output as follows −

\mathrm{Y_{0} \: = \: E \: \bar{A} \: \bar{B} \: \bar{C} \: \bar{D}}

\mathrm{Y_{1} \: = \: E \: \bar{A} \: \bar{B} \: \bar{C} \: D}

\mathrm{Y_{2} \: = \: E \: \bar{A} \: \bar{B} \: C \: \bar{D}}

\mathrm{Y_{3} \: = \: E \: \bar{A} \: \bar{B} \: C \: D}

\mathrm{Y_4 \: = \: E \: \bar{A} \: B \: \bar{C} \: \bar{D}}

\mathrm{Y_{4} \: = \: E \: \bar{A} \: B \: \bar{C} \: \bar{D}}

\mathrm{Y_5 \: = \: E \: \bar{A} \: B \: \bar{C} \: D}

\mathrm{Y_{5} \: = \: E \: \bar{A} \: B \: \bar{C} \: D}

\mathrm{Y_6 \: = \: E \: \bar{A} \: B \: C \: \bar{D}}

\mathrm{Y_{6} \: = \: E \: \bar{A} \: B \: C \: \bar{D}}

\mathrm{Y_7 \: = \: E \: \bar{A} \: B \: C \: D}

\mathrm{Y_{7} \: = \: E \: \bar{A} \: B \: C \: D}

\mathrm{Y_8 \: = \: E \: A \: \bar{B} \: \bar{C} \: \bar{D}}

\mathrm{Y_{8} \: = \: E \: A \: \bar{B} \: \bar{C} \: \bar{D}}

\mathrm{Y_9 \: = \: E \: A \: \bar{B} \: \bar{C} \: D}

\mathrm{Y_{9} \: = \: E \: A \: \bar{B} \: \bar{C} \: D}

\mathrm{Y_{10} \: = \: E \: A \: \bar{B} \: C \: \bar{D}}

\mathrm{Y_{11} \: = \: E \: A \: \bar{B} \: C \: D}

\mathrm{Y_{12} \: = \: E \: A \: B \: \bar{C} \: \bar{D}}

\mathrm{Y_{13} \: = \: E \: A \: B \: \bar{C} \: D}

\mathrm{Y_{14} \: = \: E \: A \: B \: C \: \bar{D}}

\mathrm{Y_{15} \: = \: E \: A \: B \: C \: D}

我们可以用与 2 到 4 解码器和 3 到 8 解码器相同的方式实现这些输出表达式。

We can implement these output expression in the same way as we done for the 2 to 4 decoder and 3 to 8 decoder.

现在,让我们讨论解码器的应用。

Now, let us discuss the applications of decoders.

Applications of Decoders

在仅在特定输入编码组合出现时才激活一个输出或一组输出的情况下,使用解码器。下面列出了一些解码器的重要应用:

Decoders are used in the cases where an output or a collection of outputs is to be activated only on the occurrence of a particular combination of input codes. Some important applications of decoders are listed below −

  1. Decoders are used for code conversions.

  2. Decoders are extensively used in memory systems of computers.

  3. Decoders are also used for de-multiplexing or data distribution.

  4. Decoders are also used in data routing applications where very short propagation delay is required.

  5. Decoder may also be used for timing or sequencing purposes.

  6. Decoders are also utilized to turn on and off digital devices at a specific time.

有关解码器及其在数字电子系统中的应用,就是这些。

This is all about decoder and its applications in digital electronic systems.