Digital-electronics 简明教程
Half Adder in Digital Electronics
Addition 是计算机、计算器等不同电子设备执行的最基本操作之一。执行两个或多个数字（更具体地说是二进制数）相加的电子电路称为 adder 。由于逻辑电路使用二进制数字系统执行操作，因此加法器被称为 binary adder 。
Addition is one of the most basic operations performed by different electronic devices like computers, calculators, etc. The electronic circuit that performs the addition of two or more numbers, more specifically binary numbers, is called as adder. Since, the logic circuits use binary number system to perform the operations, hence the adder is referred to as binary adder
根据电路可以相加的位数，加法器（或二进制加法器）分为两种类型：
Depending on the number of bits that the circuit can add, adders (or binary adders) are of two types −
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Half Adder
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Full Adder
在本文中，我们将讨论 half adder 、其定义、电路图、真值表、卡诺图、特征方程和应用。
In this article, we will discuss the half adder, its definition, circuit diagram, truth table, kmap, characteristic equations, and applications.
What is a Half-Adder?
设计用于相加两个二进制位组合逻辑电路称为 half adder 。半加法器提供输出以及进位值（如果有）。半加法器电路通过连接异或门和与门来设计。它有两个输入端和分别用于和和进位的两个输出端。半加法器的框图和电路图如图 1 所示。
A combinational logic circuit which is designed to add two binary digits is called as a half adder. The half adder provides the output along with a carry value (if any). The half adder circuit is designed by connecting an EX-OR gate and one AND gate. It has two input terminals and two output terminals for sum and carry. The block diagram and circuit diagram of a half adder are shown in Figure-1.
从半加法器的逻辑电路图中可以清楚地看出，A 和 B 是两个输入位，S 是输出和，C 是输出进位位。
From the logic circuit diagram of half adder, it is clear that A and B are the two input bits, S is the output sum, and C is the output carry bit.
在半加法器的情况下，异或门的输出是这两个位的和，与门的输出是进位。虽然在一个加法中获得的进位不会转发到下一个加法中，因此它被称为半加法器。
In the case of a half adder, the output of the EX-OR gate is the sum of two bits and the output of the AND gate is the carry. Although, the carry obtained in one addition will not be forwarded in the next addition because of this it is known as half adder.
Operation of Half Adder
半加法器根据二进制加法的规则相加两个二进制位。这些规则如下：
Half adder adds two binary digits according to the rules of binary addition. These rules are as follows −
\mathrm{0 \: + \: 0 \: = \: 0}
\mathrm{0 \: + \: 1 \: = \: 1}
\mathrm{1 \: + \: 0 \: = \: 1}
\mathrm{1 \: + \: 1 \: = \: 10 \: (和 \: = \: 0 \: \& \: 进位 \: = \: 1)}
\mathrm{1 \: + \: 1 \: = \: 10 \: (Sum \: = \: 0 \: \& \: Carry \: = \: 1)}
根据这些二进制加法规则，我们可以看到前三个操作产生的和的长度为一位数，而在最后一个操作（1 和 1）的情况下，和由两位数组成。这里，此结果的最高有效位 (MSB) 称为进位（为 1），最低有效位 (LSB) 称为和（为 0）。
According to these rules of binary addition, we can see that the first three operations produce a sum whose length is one digit, whereas in the case of last operation (1 and 1), the sum consists of two digits. Here, the MSB (most significant bit) of this result is called a carry (which is 1) and the LSB (least significant bit) is called the sum (which is 0).
Truth Table of Half Adder
真理表是一种给出了逻辑电路的输入与输出之间关系的表格，并解释了该电路的操作。以下是半加法的真值表：-
Truth table is one that gives the relationship between inputs and outputs of a logic circuit and explains the operation of the circuit. The following is the truth table of the half-adder −
Inputs |
Outputs |
A |
B |
S (Sum) |
C (Carry) |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
K-Map for Half Adder
我们可以使用 K-Map（卡诺图）来简化布尔代数，以便确定半加法器电路的和位（S）和输出进位位 © 的方程式。
We can use the K-Map (Karnaugh Map), a method for simplifying Boolean algebra, to determine equations of the sum bit (S) and the output carry bit © of the half adder circuit.
半加法器的 K-Map 如图 2 所示。
The k-map for half adder circuit is shown in Figure-2.
Characteristic Equations of Half-Adder
半加法器的特征方程式，即和 (S) 和进位 © 的方程式是根据二进制加法的规则得出的。这些方程式如下所示：-
The characteristic equations of half adder, i.e., equations of sum (S) and carry © are obtained according to the rules of binary addition. These equations are given below −
半加法器的和（S）是 A 和 B 的异或。因此，
The sum (S) of the half-adder is the XOR of A and B. Thus,
\text{和：S = A XOR B = AB' + A’B}
\mathrm{Sum, \: S \: = \: A \: \oplus B \: = \: AB' \: + \: A’B }
半加法器的进位（C）是 A 和 B 的与。因此，
The carry © of the half-adder is the AND of A and B. Therefore,
\text{进位：C = A AND B}
\mathrm{Carry, \: C \: = \: A \cdot B }
Applications of Half Adder
以下是半加法器的一些重要应用：-
The following are some important applications of half adder −
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Half adder is used in ALU (Arithmetic Logic Unit) of computer processors to add binary bits.
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Half adder is used to realize full adder circuit.
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Half adder is used in calculators.
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Half adder is used to calculate addresses and tables.
Conclusion
从上述讨论中，我们可以得出结论：半加法器是在不同电子设备中用于执行两个二进制数字加法运算的基本算术电路之一。半加法器的主要缺点是它不能在前面的级中添加获得的进位。为了克服这一缺点，电子系统中使用了全加法器。
From the above discussion, we can conclude that half adders are one of the basic arithmetic circuits used in different electronic devices to perform addition of two binary digits. The major drawback of a half adder is that it cannot add the carry obtained from the addition of the previous stage. To overcome this drawback, full adders are used in electronic systems.