Digital-electronics 简明教程
Digital Electronics - N-bit Parallel Adders
让我们从对二进制加法器和二进制加法的规则进行简要介绍开始这篇文章。在数字电子学中， adder 或 binary adder 是执行两个或多个二进制数位相加的组合数字电路。两个位的二进制加法通过遵循以下四个规则执行 −
Let us stat this article with a brief introduction of binary adders and rules of binary addition. In digital electronics, an adder or binary adder is a combinational digital circuit which performs the addition of two or more binary digits. The binary addition of two bits is performed by following these four rules −
\mathrm{0 \: + \: 0 \: = \: 0}
\mathrm{0 \: + \: 1 \: = \: 1}
\mathrm{1 \: + \: 0 \: = \: 1}
\(\mathrm{1 \: + \: 1 \: = \: 10 (和 \: = \: 0; 进位 \: = \: 1)}
\mathrm{1 \: + \: 1 \: = \: 10 (Sum \: = \: 0; Carry \: = \: 1)}
前三个运算的和的位长是一个二进制数位。但是，最后一个组合的和，即被加数和加数都等于 1 时，二进制和由两个二进制数位组成，即和位和进位位。最重要的位是进位位，而最低重要的位是和位。
The first three operations produce a sum whose bit length is one binary digit. But, the sum of last combination, i.e. when augend and addend both are equal to 1, the binary sum consists of two binary digits namely, sum bit and carry bit. The most significant bit is the carry bit, while the least significant bit is the sum bit.
我们还需要了解全加器电路，以便更好地理解 N 位并行加法器的实现和操作。全加器及其框图和真值表如下所述。
We also require the knowledge of full-adder circuit for better understanding of the implementation and operation of an N-bit parallel adder. The full-adder along with its block diagram and truth table is describe below.
What is Full Adder?
将两个位和一位进位相加并产生一位和位和一位进位位作为输出的组合数字电路称为 full adder (FA) 。
A combination digital circuit that adds two bits and a carry bit and produces a sum bit and a carry bit as output is referred to as a full adder (FA).
换句话说，可以加三个输入位并产生两个输出位（即和位和进位位）的二进制加法器电路称为全加器。全加器的框图如图 1 所示。
In other words, a binary adder circuit that can add three input bits and produces two output bits, i.e. sum bit and carry bit is called full adder. The block diagram of a full adder is shown in Figure-1.
这里，A 和 B 是输入位，Cin 是前一个和的输入进位位，S 是输出和位，Cout 是输出进位位。
Here, A and B are the input bits, Cin is the input carry bit from previous sum, S is the output sum bit, and Cout is the output carry bit.
全加器电路的操作可以很容易地从其以下给出的真值表中理解。
The operation of the full adder circuit can be understood easily from its truth table which is given below.
Input |
Output |
A |
B |
Cin |
S |
Cout |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
1 |
0 |
1 |
0 |
0 |
1 |
1 |
0 |
1 |
1 |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
1 |
1 |
1 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
现在，让我们讨论使用全加器实现 N 位并行加法器。
Now, let us discuss the realization of an N-bit parallel adder using full adders.
N-Bit Parallel Adder
Parallel adder 是用来加两个有 N 位的二进制数的二进制加法器电路（例如，要加 4 位二进制数，我们使用 4 位并行加法器，以此类推）。顾名思义，并行加法器是一个数字组合电路，它以并行形式加两个二进制数，并以并行形式生成这些二进制数的算术和。
Parallel adder is a binary adder circuit implemented to add two binary number having N-bits (for example, to add 4-bit binary numbers, we use 4- bit parallel adder, and so on). As its name implies, the parallel adder is a digital combinational circuit that adds two binary numbers in parallel form and generates the arithmetic sum of those binary numbers in parallel form.
正如我们上面已经提到的，全加器只能执行两个一个位二进制数的加法，这些二进制数由两个输入位和一个输入进位位组成，即三位相加。但在实际操作中，我们必须加长度超过一位的二进制数。为了加这种二进制数，我们使用并行二进制加法器，它能够加任何位长的两个二进制数，例如 4 位、5 位等。
As we already mentioned above that a full adder can perform addition of only two one-bit binary numbers consisting of two input bits and one input carry bit, i.e. addition of three bits. But in actual practice, we have to add such binary numbers whose length is more than one bit. To add such binary numbers, we use parallel binary adder which is capable of adding the two binary numbers of any bit length such as 4-bit, 5-bit, etc.
我们可以通过以链式连接方式连接全加器来实现一个 N 位并行加法器。使用全加器的 N 位并行加法器的框图表示如图 2 所示。
We can implement an N-bit parallel adder with the help of full-adders connected in a chain fashion. The block diagram representation of an N-bit parallel adder using full adders is shown in Figure-2.
从 N 位并行加法器的框图可以看出，每个全加器的进位输出连接到链中更高一级的全加器的进位输入端。
From the block diagram of the N-bit parallel adder, it can be seen that the carry output from each full-adder is connected to the carry input terminal of the next higher level full-adder in the chain.
实现并行加法器所需的全加器数量由要加的两个二进制数中的位数决定。因此，一个 N 位并行加法器需要 N 个全加器来执行并行加法。例如，一个 2 位并行加法器需要 2 个全加器，4 位并行加法器由 4 个全加器组成，以此类推。
The number of full-adder to realize a parallel adder is determined from the number of bits in the two binary numbers to be added. Therefore, an N-bit parallel adder requires N full-adders to perform the addition in parallel form. For example, a 2-bit parallel adder requires 2 full adders, 4-bit parallel adder consists of 4 full adders, and so on.
Operation of N-Bit Parallel Adder Circuit
图 2 中所示的 N 位并行加法器的功能可以用以下步骤描述 −
The working of the N-bit parallel adder shown in figure-2 can be described in the following steps −
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Initially, the full adder FA1 adds two input bits A1 and B1 along with an input carry bit Cin, and it generates the output sum bit S1 and the carry bit C1 which is forwarded to the next adder (FA2) in the chain. The sum bit S1 is the least significant bit of the output sum.
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At the next stage, the full adder circuit FA2 becomes active and adds input bits A2 and B2 along with C1. It generates the sum bit S2 which is the second bit of the output sum, and the carry bit C2 that is connected to the next full adder FA3 in the chain.
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This process will continue till the last full adder, i.e. FAn in the chain. The full adder uses carry input C(n-1) to add with the input bits An and Bn to produce the last bit of the output sum Sn and the last output carry bit Cn.
Advantages of Parallel Adder
并行加法器的一些重要优点如下所列 −
Some important advantages of parallel adder are listed below −
-
The parallel adder adds bits simultaneously.
-
It makes addition of binary numbers fast.
-
Parallel adder is more economical.
Disadvantages of Parallel Adder
并行加法器的主要缺点在于传播延迟。这是因为在并行加法器中，必须将来自前一次加法的进位传播到下一个加法器，而这需要花费一些时间。这会在加法中造成严重的传播延迟。这种传播延迟与二进制数字中的位数成正比。
The major disadvantage of the parallel adder is propagation delay. Since, in the parallel adder, carry from previous addition has to be propagated to the next adder which takes some time. This cause a significant propagation delay in the addition. This propagation delay is directly proportional to the number of bits in the binary numbers.
Applications of Parallel Adder
并行加法器的重要应用包括：
The important applications of parallel adders are listed below −
-
Parallel adders are used in arithmetic logic units that are used for heavy computing applications.
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Parallel adders are also used in parallel cellular automatic machines for parallel computing.
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Parallel adders are utilized for conversion of BCD into excess-1 code.
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Parallel adders are also used for the analysis of multiplication algorithms.
Conclusion
我们可以得出结论，n 位并行加法器是一种组合数字电路，使用 n 个全加器来并行对两个二进制数字进行加法。并行加法器可以同时对多个位进行加法，因此可以提高二进制加法的速度。
We can conclude that the n-bit parallel adder is a combination digital circuit which is implemented using n full-adders to add two binary numbers in parallel form. The parallel adder performs addition of bits simultaneously, hence it increases the speed of binary addition.