Digital-electronics 简明教程
Half Subtractor using NAND Gates
在数字电子学中， subtractor 是执行两个二进制数减法的组合逻辑电路。但是，可以通过取 1 的或 2 的补数来使用加法器电路执行二进制数减法。但是，我们还可以实现专用电路来执行两个二进制数的减法。
In digital electronics, a subtractor is a combinational logic circuit that performs the subtraction of two binary numbers. However, the subtraction of binary number can be performed using adder circuits by taking 1’s or 2’s compliments. But, we may also realize a dedicate circuit to perform the subtraction of two binary numbers.
在两个二进制数的减法中，数字的每个被减位都在其相应的显着减数位中减去以形成差位。在减法的过程中，如果减数位小于被减数位，则从下一个位置借用 1。根据输入的位数，减法器有两种类型，即 Half Subtractor 和 Full Subtractor 。
In the subtraction of two binary numbers, each subtrahend bit of the number is subtracted from its corresponding significant minuend bit to form a difference bit. During the subtraction, if the minuend bit is smaller than the subtrahend bit, then a 1 is borrowed from the next position. Depending upon the number of bits taken as input, there are two types of subtractors namely, Half Subtractor and Full Subtractor.
半减法器是一种将两个二进制数字作为输入并给出差位和借位（如果有）作为输出的减法器。
A half subtractor is one which takes two binary digits as input and gives a difference bit and a borrow bit (if any) as output.
另一方面，全减法器是一种将三个位作为输入（即两个是输入位，一个是从前一级的输入借位）并给出差位和输出借位作为输出的减法器。
On the other hand, a full subtractor is one that takes three bits as input, i.e. two are the input bits and one is the input borrow bit from the previous stage, and gives a difference bit and a output borrow bit as the output.
由于减法器是一种组合逻辑电路，即它由逻辑门制成。我们可以使用不同类型的逻辑门（如 AND、OR、NOT、NAND、NOR 等）实现全加法器电路。
Since a subtractor is a combinational logic circuit, i.e. it is made of logic gates. We can realize a full adder circuit using different types of logic gates like AND, OR, NOT, NAND, NOR, etc.
这里，我们将讨论 implementation of a half subtractor using NAND gates 。但在那之前，我们先了解一下半减法器的基础知识。
Here, we will discuss the implementation of a half subtractor using NAND gates. But before that let’s have a look into the basics of the half subtractor.
What is Half Subtractor?
half-subtractor 是一个组合电路，它有两个输入和两个输出，其中一个输出是差值，另一个是借位。半减法器生成输入处的两个二进制位之间的差值，并生成借位输出（如果有的话）。在减法（A-B）中，A 称为 Minuend bit ，B 称为 Subtrahend bit 。半减法器的框图如图 1 所示。
A half-subtractor is a combinational circuit which has two inputs and two outputs where one output is difference and another is borrow bit. The half subtractor produces the difference between the two binary bits at the input and also produces a borrow output (if any). In the subtraction (A-B), A is called as Minuend bit and B is called as Subtrahend bit. The block diagram of the half subtractor is shown in Figure-1.
在这里，A 和 B 是输入变量（二进制位），d 是输出差值位，b 是借位。借助真值表，我们可以理解半减法器的操作。
Here, A and B are the input variables (binary digits) and d is the output difference bit and b is the borrow bit. We can understand the operation of a half subtractor with the help of its truth table.
Truth Table of Half Subtractor
以下是以半减法器为核心的真值表 -
The following is the truth table the half subtractor −
Inputs |
Outputs |
A |
B |
D (Difference) |
B (Borrow) |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
0 |
0 |
使用此真值表，我们可以确定半减法器的输出方程。以下是差值位 (d) 和借位 (b) 的方程 -
Using this truth table, we can determine the output equation of the half subtractor. The following are the equations of difference bit (d) and borrow bit (b) −
Different Bit (D) −
Different Bit (D) −
\mathrm{差值, \: d \: = \: A’B \: + \: AB' \: = \: A \oplus B}
\mathrm{Difference, \: d \: = \: A’B \: + \: AB' \: = \: A \oplus B}
Borrow Bit (B)
Borrow Bit (B)
\mathrm{借位, \: b \: = \: A’B}
\mathrm{Borrow, \: b \: = \: A’B}
现在，我们来讨论使用 NAND 门实现半减法器。
Now, let us discuss the realization of half subtractor using NAND gates.
Half Subtractor Using NAND Gates
我们仅可使用 NAND 门实现半减法器的逻辑电路，如图 2 所示。
We may implement the logic circuit of half subtractor using NAND gates only as shown in figure-2.
从这个逻辑电路图中，我们可以看到实现半减法器需要 9 个 NAND 门。
From this logic circuit diagram, we can see that 9 NAND gates are required for realization of the half subtractor.
半减法器在 NAND 逻辑中的输出方程如下 -
The output equations of the half subtractor in NAND logic are as follows −
Difference Bit (D)
Difference Bit (D)
\mathrm{差值, \: d \: = \: \overline{\overline{A \cdot \: \overline{AB}} \: \cdot \: \overline{B \cdot \overline{AB}}} \ = \: A \oplus B}
\mathrm{Difference, \: d \: = \: \overline{\overline{A \cdot \: \overline{AB}} \: \cdot \: \overline{B \cdot \overline{AB}}} \ = \: A \oplus B}
Borrow Bit (B)
Borrow Bit (B)
\mathrm{借位, \: b \: = \: \overline{\overline{B \cdot \: \overline{AB}}} \: = \: \overline{A} \: B}
\mathrm{Borrow, \: b \: = \: \overline{\overline{B \cdot \: \overline{AB}}} \: = \: \overline{A} \: B}
通过这种方式，我们仅使用 NAND 门就能实现半减法器。
In this way, we can realize the half subtractor using the NAND gates only.