Digital-electronics 简明教程
Implementation of NOR Gate from NAND Gate
NOR 和 NAND 门是通用逻辑门, 使用它们我们可以实现任何逻辑门或任何其他逻辑表达式。阅读本教程, 了解如何使用 NAND 门实现 NOR 门。
NOR and NAND gates are universal logic gates, using which we can implement any logic gate or any other logical expression. Read this tutorial to find out how you can implement a NOR gate using a NAND gate.
What is a NOR Gate?
NOR Gate 是一种通用逻辑门, 因为此逻辑门可用于实现任何其他类型的逻辑门。
NOR Gate is a type of universal logic gate, because this logic gate can be used for implementation of any other type of logic gate.
NOR 表示“非 + 或”。这意味着 OR 输出取反或反转。因此, NOR 门是 OR 门和非门的组合。
NOR means "NOT + OR". That means the OR output is NOTed or inverted. Therefore, the NOR gate is a combination of OR gate and a NOT gate.
\mathrm{NOR \: Gate \: = \: OR \: Gate \:+ \: NOT \: Gate}
NOR 门是一种逻辑门, 只有当其所有输入均为低 (逻辑 0) 时, 其输出才为高 (逻辑 1), 而且即使其任何输入变为高 (逻辑 1), 它也给出低 (逻辑 0) 输出。双输入 NOR 门的逻辑符号如图 1 所示。
A NOR gate is a type of logic gate whose output is HIGH (Logic 1), only when all its inputs are LOW (Logic 0), and it gives an output LOW (Logic 0), even if any of its inputs become HIGH (Logic 1). The logic symbol of a two input NOR gate is shown in Figure-1.
Output Equation of NOR Gate
如果 A 和 B 是输入变量, 并且 Y 是 NOR 门的输出变量, 则 NOR 门的输出由以下公式给出：
If A and B are the input variables and Y is the output variable of the NOR gate, then the output of the NOR gate is given by,
\mathrm{Y \: = \: \overline{A \: + \: B} \: = \: (A \: + \: B)'}
“Y 等于 A 加 B 杠”。
It is read as "Y is equal to A plus B whole bar".
What is a NAND Gate?
NAND 门是一种通用逻辑门。通用逻辑门是可以用来实现任何类型的逻辑表达式或任何其它类型逻辑门的逻辑门。
The NAND Gate is a type of universal logic gate. Where, a universal logic gate is one that can be used to realize any kind logical expression or any other type of logic gate.
NAND 门实际上是两个基本逻辑门的组合，即 AND 门和 NOT 门，即，
A NAND gate is basically a combination of two basic logic gates namely AND gate and NOT gate, i.e.,
\mathrm{NAND \: Logic \: = \: AND \: Logic \: = \: NOT \: Logic}
NAND 门是一种当所有输入都是 HIGH 时输出为 LOW（逻辑 0），当任何一种输入为 LOW（逻辑 0）时输出为 HIGH（逻辑 1）的逻辑门。因此，NAND 门的操作与 AND 门相反。一个两个输入的 NAND 门的逻辑符号如图 2 所示。
A NAND gate is the type of logic gate whose output is LOW (Logic 0) when all its inputs are high, and its output is HIGH (Logic 1), when any of its inputs is LOW (Logic 0). Therefore, the operation of the NAND gate is opposite that of the AND gate. The logic symbol of a two input NAND gate is shown in Figure-2.
Output Equation of NAND Gate
如果 A 和 B 是一个 NAND 门的输入变量，Y 是输出变量，则其输出可表示为
If A and B are the input variables and Y is the output variable of the NAND gate, then its output is given by,
\mathrm{Y \: = \: \overline{A \: \cdot \: B} \: = \: (A \: + \: B)'}
它被解释为“Y 等于 A 点 B 全整”。
It is read as "Y is equal to A.B whole bar".
Implementation of NOR Gate from NAND Gate
如上所述，NAND 门是通用逻辑门，因此，它可用于实现任何其他逻辑门。使用 NAND 门实现 NOR 门如图 3 所示。
As mentioned above, the NAND gate is a universal logic gate, therefore, it can be used to realize the any other logic gate. The implementation of NOR gate using the NAND gate is shown in Figure-3.
从逻辑电路来看，很明显，仅使用 NAND 门实现 NOR 门时，我们需要 4 个 NAND 门。前两个 NAND 门执行输入变量 A 和 B 的补码，第三个 NAND 门生成补码输入的 NAND 输出，即 A' 和 B'。最后，第四个 NAND 门再次作为反相器并产生输出 Y。此输出 Y 等效于 NOR 门的输出。
From the logic circuit, it is clear that for the implementation of NOR gate using NAND gates only, we require 4 NAND gates. The first two NAND gates perform the complement of input variables A and B, the third NAND gate produce the NAND output of the complemented inputs, i.e. A' and B'. Finally, the fourth NAND gate again operates as an inverter and produce the output Y. This output Y is the equivalent to the output of the NOR gate.
Output Equation
第一个和第二个 NAND 门的输出为，
The output of the first and second NAND gates is,
\mathrm{Y_{1} \: = \: \bar{A} \:\: and \:\: Y_{2} \: = \: \bar{B}}
第三个 NAND 门的输出为，
The output of the third NAND gates is,
\mathrm{Y_{3} \: = \: \overline{\bar{A} \: \cdot \: \bar{B}} \: = \: A \: + \: B}
第四个 NAND 门的输出为，
The output of the fourth NAND gate is,
\mathrm{Y \: = \: \overline{A \: + \: B}}
因此，这是 NOR 门的输出。通过这种方式，我们只能使用 NAND 门实现 NOR 门。
Hence, this is the output of a NOR Gate. In this way, we can implement a NOR gate using NAND gates only.