Digital-electronics 简明教程
Implementation of XNOR Gate from NAND Gate
众所周知，NAND 门是一种通用逻辑门，我们可以使用它来实现任何其他类型的逻辑门或逻辑表达式。阅读本教程以了解如何仅使用 NAND 门来实现一个 XNOR 门。让我们从 XNOR 和 NAND 门的基本概述开始。
As we know, the NAND Gate is a universal logic gate, using which we can implement any other type of logic gate or logical expression. Read this tutorial to find out how you can implement an XNOR gate using only NAND gates. Let’s start with a basic overview of XNOR and NAND gates.
What is an XNOR Gate?
XNOR (Exclusive-NOR) Gate 是一种衍生逻辑门。XNOR 门是一种逻辑门，它有两个输入和一个输出。当 XNOR 门的两个输入相等（即均为高电平 (逻辑 1) 或低电平 (逻辑 0)）时，它产生一个高电平 (逻辑 1) 输出。
The XNOR (Exclusive-NOR) Gate is a type of derived logic gate. The XNOR gate is a logic gate that has two inputs and one output. The XNOR gate produces a HIGH (Logic 1) output when both of its inputs are equal, i.e. either HIGH (Logic 1) or LOW (Logic 0).
当 XNOR 门的输入不同（即一个为高电平 (逻辑 1) 而另一个为低电平 (逻辑 0)）时，XNOR 门的输出为低电平 (逻辑 0) 状态。XNOR 门的逻辑符号如图 1 所示。
When the inputs of the XNOR gate are different, i.e., one is HIGH (Logic 1) and another is LOW (Logic 0), then the output of the XNOR gate is a LOW (Logic 0) state. The logic symbol of the XNOR gate is shown in Figure-1.
因此，仅当 XNOR 门的两个输入相等时，它才会产生高电平 (逻辑 1) 输出。因此，XNOR 门也被称为 "equality detector" 。
Hence, the XNOR gate produces an output HIGH (Logic 1) only when both of its inputs are equal. Thus, the XNOR gate is also known as "equality detector".
XNOR 门的输出由以下公式给出：
The output of the XNOR gate is given by,
\mathrm{Y \: = \: A \odot B \: = \: AB \: + \: \bar{A} \: \bar{B}}
其中，A 和 B 是 XNOR 门的两个输入变量，Y 是 XNOR 门的输出变量。XNOR 门的输出表达式可解读为 Y 等于 A 与非 B。
Where, A and B are the two input variables to the XNOR gate, Y is the output variable of the XNOR gate. The output expression of the XNOR gate is read as Y is equal to A ex-nor B.
What is a NAND Gate?
NAND Gate 是一种通用逻辑门。其中，通用逻辑门可以用于实现任何类型的逻辑表达式或任何其他类型的逻辑门。
The NAND Gate is a type of universal logic gate. Where, a universal logic gate is one that can be used to realize any kind logical expression or any other type of logic gate.
NAND 门实际上是两个基本逻辑门的组合，即 AND 门和 NOT 门，即，
A NAND gate is basically a combination of two basic logic gates namely AND gate and NOT gate, i.e.,
\mathrm{NAND \: Logic \: = \: AND \:Logic \: + \: NOT \: Logic}
NAND 门是一种当所有输入都是 HIGH 时输出为 LOW（逻辑 0），当任何一种输入为 LOW（逻辑 0）时输出为 HIGH（逻辑 1）的逻辑门。因此，NAND 门的操作与 AND 门相反。一个两个输入的 NAND 门的逻辑符号如图 2 所示。
A NAND gate is the type of logic gate whose output is LOW (Logic 0) when all its inputs are high, and its output is HIGH (Logic 1), when any of its inputs is LOW (Logic 0). Therefore, the operation of the NAND gate is opposite that of the AND gate. The logic symbol of a two input NAND gate is shown in Figure-2.
Output Equation of NAND Gate
如果 A 和 B 是一个 NAND 门的输入变量，Y 是输出变量，则其输出可表示为
If A and B are the input variables and Y is the output variable of the NAND gate, then its output is given by,
\mathrm{Y \: = \: \overline{A \cdot B} \: = \: (A \cdot B)'}
它表示为“Y 等于 A·B 上划线”。
It is read as "Y is equal to A·B whole bar".
Implementation of XNOR Gate from NAND Gate
如上所述，NAND 门是通用逻辑，我们可以用它来实现任何其他类型的逻辑门。使用 NAND 门实现 XNOR 门如下图 3 所示。
As discussed above, the NAND gate is a universal logic, using which we can implement any other type of logic gate. The realization of XNOR gate using NAND gates is shown in Figure-3.
从仅使用 NAND 门的 XNOR 门逻辑电路图可以清楚地看出，我们需要 5 个 NAND 门。
From the logic circuit diagram of the XNOR gate using NAND gates only, it is clear that we require 5 NAND gates.
接下来，让我们了解该 NAND 逻辑电路如何发挥作用以产生与 XNOR 门等效的输出 −
Now, let us understand how this NAND logic circuit functions to produce an output equivalent to the XNOR gate −
第一个 NAND 门的输出为：
The output of the first NAND gate is,
\mathrm{Y_{1} \: = \: \overline{A \: B}}
第二个和第三个 NAND 门的输出为：
The outputs of the secondary and third NAND gates are,
\mathrm{Y_{2} \: = \: \overline{A \cdot \: \overline{AB}}}
\mathrm{Y_{3} \: = \: \overline{B \cdot \: \overline{AB}}}
这两个输出（Y2 和 Y3）连接到第四个 NAND 门。该 NAND 门将产生输出，即：
These two outputs (Y2 and Y3) are connected to the fourth NAND gate. This NAND gate will produce an output which is,
\mathrm{Y \: = \: \overline{\overline{A \cdot \: \overline{AB}} \cdot \overline{B \cdot \overline{AB}}}}
\mathrm{\Rightarrow \: Y \: = \: A \cdot \overline{AB} \: + \: B \cdot \overline{AB} \: = \: A(\bar{A} \: + \: \bar{B}) \: + \: B(\bar{A} \: + \: \bar{B})}
\mathrm{\Rightarrow \: Y \: = \: A \: \bar{A} \: + \: A \: \bar{B} \: + \: \bar{A} \: B \: + \: B \: \bar{B}}
\mathrm{\therefore \: Y \: = \: A \: \bar{B} \: + \: \bar{A} \:B \: = \: A \oplus B}
最后，第四个 NAND 门的输出输入到作为反相器的第五个 NAND 门，并产生与 XNOR 门等效的输出，即，
Finally, the output of the fourth NAND gate is input to the fifth NAND gate that functions as an inverter, and produces an output equivalent to the XNOR gate, i.e.,
\mathrm{Y \: = \: \overline{A \oplus B} \: = \: A \odot B}
这是异或门 (XNOR) 的输出。因此，我们可以仅使用与非门实现一个异或门。
This is the output of the XNOR gate. Therefore, in this way, we can implement the XNOR gate from NAND gates only.