Digital-electronics 简明教程
Implementation of XOR Gate from NAND Gate
NAND 门是一种通用逻辑门，我们可以使用它实现任何其他类型的逻辑门或逻辑表达式。阅读本教程以了解如何仅使用 NAND 门实现异或门。让我们从对异或门和 NAND 门的基本概述入手
The NAND Gate is a universal logic gate, using which we can implement any other type of logic gate or logical expression. Read this tutorial to understand how you can implement a XOR gate using only NAND gates. Let’s start with a basic overview of XOR and NAND gates
What is a XOR Gate?
{s0} 是一种派生逻辑门。异或门是一种具有两个输入和一个输出的逻辑门。当且仅当异或门的两个输入中的一个为 HIGH（逻辑 1）时，异或门会产生 HIGH（逻辑 1）输出。当异或门的两个输入均为 HIGH（逻辑 1）或 LOW（逻辑 0）时，异或门的输出则为 LOW（逻辑 0）状态。异或门的逻辑符号 a 如图 1 所示。
The XOR (Exclusive-OR) Gate is a type of derived logic gate. The XOR gate is a logic gate that has two inputs and one output. The XOR gate produces a HIGH (Logic 1) output when one and only one of its two inputs are HIGH (Logic 1). When both inputs of the XOR gate are HIGH (Logic 1) or LOW (Logic 0), then the output of the XOR gate is a LOW (Logic 0) state. The logic symbol of the XOR gate a is shown in Figure-1.
因此，异或门仅在其输入不相等时才产生 HIGH 输出。因此，异或门也被称为 {s1} 或 {s2}。
Hence, the XOR gate produces an output HIGH only when its inputs are not equal. Therefore, the XOR gate is also known as "anti-coincidence gate" or "inequality detector".
Output Equation of XOR Gate
异或门的输出是其输入的模求和，即
The output of the XOR gate is the modulo sum of its inputs, i.e.,
\mathrm{Y \: = \: A \oplus B \: = \: A \: \bar{B} \: + \: \bar{A} \: B}
其中 A 和 B 是异或门的两个输入变量，Y 是异或门的输出变量。异或门的输出表达式读取为 Y 等于 A 异或 B。
Where, A and B are the two input variables to the XOR gate, Y is the output variable of the XOR gate. The output expression of the XOR gate is read as Y is equal to A ex-or B.
What is a NAND Gate?
A NAND Gate 是一种通用逻辑门，可用于实现任何类型的逻辑表达式或任何其他类型的逻辑门。NAND 门基本上将两个基本逻辑门相结合，即 AND 门和 NOT 门，即
A NAND Gate is a type of universal logic gate that can be used to realize any kind logical expression or any other type of logic gate. A NAND gate is basically a combination of two basic logic gates namely, AND gate and NOT gate, i.e.,
\mathrm{NAND \: Logic \: = \: AND \: Logic \: = \: NOT \: Logic}
NAND 门是一种当所有输入都是 HIGH 时输出为 LOW（逻辑 0），当任何一种输入为 LOW（逻辑 0）时输出为 HIGH（逻辑 1）的逻辑门。因此，NAND 门的操作与 AND 门相反。一个两个输入的 NAND 门的逻辑符号如图 2 所示。
A NAND gate is the type of logic gate whose output is LOW (Logic 0) when all its inputs are high, and its output is HIGH (Logic 1), when any of its inputs is LOW (Logic 0). Therefore, the operation of the NAND gate is opposite that of the AND gate. The logic symbol of a two input NAND gate is shown in Figure-2.
Output Equation of NAND Gate
如果 A 和 B 是 NAND 门的输入变量，Y 是 NAND 门的输出变量，则其输出由下式给出：
If A and B are the input variables and Y is the output variable of the NAND gate, then its output is given by
\mathrm{Y \: = \: \overline{A \cdot B} \: = \: (A \cdot B)'}
它表示为“Y 等于 A·B 上划线”。
It is read as "Y is equal to A·B whole bar".
Implementation of XOR Gate from NAND Gate
如上所述，NAND 门是一种通用逻辑，因此我们可以使用它来实现任何其他逻辑门。图 3 显示了仅使用 NAND 门如何实现异或门。
As discussed above, the NAND gate is a universal logic, hence, using which we may implement any other logic gate. Figure-3 shows how you can implement a XOR gate using only NAND gates.
仅使用 NAND 门的异或门的逻辑电路图清楚地表明，我们需要 4 个 NAND 门。
From the logic circuit diagram of the XOR gate using NAND gates only, it is clear that we require 4 NAND gates.
现在，让我们了解此 NAND 逻辑电路如何运作以产生等于异或门的输出。
Now, let us understand how this NAND logic circuit functions to produce an output equivalent to the XOR gate.
第一个 NAND 门的输出为：
The output of the first NAND gate is,
\mathrm{Y_{1} \: = \: \overline{A \: B}}
第二个和第三个 NAND 门的输出为：
The outputs of the secondary and third NAND gates are,
\mathrm{Y_{2} \: = \: \overline{A \cdot \overline{AB}}}
\mathrm{Y_{3} \: = \: \overline{B \cdot \overline{AB}}}
最后，这两个输出（Y2 和 Y3）连接到第四个 NAND 门。此 NAND 门将产生一个输出，即
Finally, these two outputs (Y2 and Y3) are connected to the fourth NAND gate. This NAND gate will produce an output which is,
\mathrmmathrm{Y \: = \: \overline{\overline{A \cdot \overline{AB}} \cdot \overline{B \cdot \overline{AB}}}}
\mathrm{Y \: = \: \overline{\overline{A \cdot \overline{AB}} \cdot \overline{B \cdot \overline{AB}}}}
\mathrm{\Rightarrow \: Y \: = \: A \cdot \overline{AB} \: + \: B \cdot \overline{AB} \: = \: A(\bar{A} \: + \: \bar{B}) \: + \: B(\bar{A} \: + \: \bar{B})}
\mathrm{\Rightarrow \: Y \: = \: A \: \bar{A} \: + \: A \: \bar{B} \: + \: \bar{A} \: B \: + \: B \: \bar{B}}
\mathrm{\therefore \: Y \: = \: A \: \bar{B} \: + \: \bar{A} \: B \: = \: A \oplus B}
这是异或门的输出。因此，通过这种方式，我们仅使用 NAND 门就可以实现异或门。
This is the output of the XOR gate. Hence, in this way, we can implement the XOR gate from NAND gates only.