Digital-electronics 简明教程
Parallel Adder and Parallel Subtractor
在数字电子学中， adder 和 subtractor 是两种最基本的算术组合电路。加法器是一个组合算术电路，用于对两个或多个二进制数执行加法。而减法器是一个组合算术电路，用于对两个二进制数执行减法。
In digital electronics, adder and subtractor are the two most basic arithmetic combinational circuits. The adder is a combinational arithmetic circuit used to perform addition of two or more binary numbers. Whereas, the subtractor is a combination arithmetic circuit used to perform subtraction of two binary numbers.
根据执行二进制数加法和减法的形式，加法器和减法器分为以下类型：
Depending on the form in which the addition and subtraction of binary numbers are executed, the adder and subtractor are classified into following types −
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Serial Adder
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Parallel Adder
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Serial Subtractor
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Parallel Subtractor
本教程旨在解释并行加法器和并行减法器。但是在讨论它们之前，让我们首先讨论执行二进制加法和减法所遵循的布尔代数规则。
This tutorial is meant for explaining Parallel Adder and Parallel Subtractor. But before that let us first discuss the rules of Boolean algebra followed to perform the binary addition and subtraction.
Binary Addition
在执行二进制加法时遵循以下规则：
The following rules are followed while performing binary addition −
Binary Digit A |
Binary Digit B |
Sum (A + B) |
Carry |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
Binary Subtraction
在执行二进制减法时遵循以下规则：
The following rules are to be followed while performing binary subtraction −
Binary Digit A |
Binary Digit B |
Difference (A - B) |
Borrow |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
0 |
0 |
现在，让我们详细讨论并行加法器和并行减法器。
Now, let us discuss the parallel adder and parallel subtractor in detail.
What is Parallel Adder?
一个以并行形式对两个任意位长的二进制数进行加法并在并行形式中生成这些数的和的数字电路称为 parallel adder.
A digital circuit that adds two binary numbers of any bit length in parallel form and produces the sum of those number in parallel form is called a parallel adder.
并行加法器基本上由链式全加器组成，如图 1 所示。此处，每个全加器的输出位连接到链中下一个全加器电路的输入进位端子上。
A parallel adder basically consists of full adders in a chain form as shown in Figure 1. Here, the output bit of each full adder is connected to the input carry terminal of the next full adder circuit in the chain.
图 1 所示的并行加法器是一个 4 位并行加法器，因为它可以对两个 4 位二进制数进行加法。虽然我们可以通过增加链中全加器的数量来设计任意位数的并行加法器电路。
The parallel adder shown in Figure 1 is a 4-bit parallel adder as it can add two binary number of 4 bits. Although, we can design a parallel adder circuit for any number of bits by increasing the number of full adders in the chain.
在上面的并行加法器电路中，位 A 表示被加数位，B 表示加数位。第一个输入进位位到并行加法器是 Cin，并行加法器的输出进位位是 C4。输出和位由 S 指定。我们也可以以 IC 的形式构建并行加法器。例如，当 4 位并行加法器以 IC 形式形成时，它将具有四个端子用于被加数位，四个端子用于加数位，四个端子用于和位，以及两个端子用于输入和输出进位位。
In the above parallel adder circuit, the bit A is representing the augend bits and B is representing the addend bits. The first input carry bit to the parallel adder is Cin and the output carry bit of the parallel adder is C4. The output sum bits are designated by S. We can also construct a parallel adder in the form of an IC. For example, when the 4-bit parallel adder is formed in the IC form, then it will have four terminals for augend bits, 4 terminals for addend bits, 4 terminals for sum bits, and 2 terminals for input and output carry bits.
Working of Parallel Adder
图 1 中所示的并行加法器根据以下步骤对两个数进行二进制加法：
The parallel adder shown in figure-1 performs the binary addition of two numbers as per the following step −
Step 1 - 首先，全加器电路 FA1 对位 A1 和 B1 及输入进位位 Cin 进行加法，产生和位 S1，它是输出和的最低有效位 (LSB)。在此阶段，会生成一个进位位 C1，它被传输到链中的下一个全加法器电路。
Step 1 − Firstly, the full adder circuit FA1 adds the bits A1 and B1 along with the input carry bit Cin to produce the sum bit S1, where it is the LSB (Least Significant Bit) of the output sum. At this stage, a carry bit C1 is generated which is transferred to the next full adder circuit in the chain.
Step 2 - 全加器电路 FA2 对位 A2 和 B2 及前次加法的进位位 C1 进行加法。它产生和位 S2，它是输出和的第二位，并且还产生进位位 C2，再次转发到下一个全加器 FA3。
Step 2 − The full adder circuit FA2 adds bits A2 and B2 along with the carry bit C1 from the previous addition. It produces the sum bit S2 which is the second bit of the output sum, and a carry bit C2 is also produced which again forwarded to the next full adder FA3.
Step 3 - 全加电路 FA3 将输入位 A3 和 B3 以及前一次加法的进位位 C2 相加，产生和位 S3 和进位位 C3。
Step 3 − The full adder circuit FA3 adds inputs bits A3 and B3 along with the carry bit C2 from previous addition to produce sum bit S3 and carry bit C3.
Step 4 - 全加器 FA4 将输入位 A4 和 B4 以及来自 FA3 的进位位 C3 相加，它产生最后一个和位 S4 和最后一个进位位 C4。
Step 4 − The full adder FA4 adds input bits A4 and B4 along with the carry bit C3 forward from FA3. It generates the last sum bit S4 and a last carry bit C4.
Step 5 - 然后，并行加法器的输出和由下式给出：
Step 5 − The output sum of the parallel adder is then given by,
\mathrm{S_{out} \: = \: C_{4} \: S_{4} \: S_{3} \: S_{2} \: S_{1}}
What is Parallel Subtractor?
用于以并行形式查找两个二进制数的算术差的数字运算电路称为 parallel subtractor 。
A digital arithmetic circuit which is used to find the arithmetic difference of two binary numbers in parallel form is called a parallel subtractor.
我们可以通过多种方式实现并行减法器，例如组合半减法器和全减法器，所有全减法器，所有全加器等。在此，我们使用所有全加器实现了 4 位并行减法器，其中被减数位被取反，如图 2 所示。
We can implement a parallel subtractor in several ways such as combining half subtractors and full subtractors, all full subtractors, all full adders, etc. Here, we have realized a 4-bit parallel subtractor using all full adders with subtrahend bit complemented as shown in Figure 2.
这是 4 位并行减法器，但是，我们可以通过在图 2 所示电路的链中添加任意数量的全加器来实现并行减法器。
This is the 4-bit parallel subtractor, however, we can implement a parallel subtractor by adding any number of full adders in the chain of the circuit shown in figure-2.
两个二进制数的二进制减法可以通过 1 的补码或 2 的补码方便地完成。其中，补码方法将减法运算转换为简单的加法运算。
The binary subtraction of two binary numbers can be conveniently accomplished by means of 1’s or 2’s complement. Where, the complement method converts the subtraction operation in simple addition operation.
二进制数的 2 的补码是通过取 1 的补码并在最小有效位对中添加 1 来获得的。1 的补码可以在非门（反相器）的帮助下实现。
The 2’s complement of binary numbers is obtained by taking the 1’s complement and adding 1 to the least significant pair of bits. The 1’s complement can be implemented with the help of a NOT gate (inverter).
Working of Parallel Subtractor
上图 2 中所示的并行减法器根据以下步骤执行两个二进制数的减法：
The parallel subtractor shown in above figure-2 carries out the subtraction of two binary numbers as per the following steps −
Step 1 - 首先，使用反相器获得位 B1 的 1 的补码，并添加 1 (Cin) 来获得位 B1 的 2 的补码。然后，将此 2 的补码 B1 进一步添加到 A1。这将产生由 S1 指定的输出差的第一位和连到 FA2 的输入进位的进位位 C1。
Step 1 − Firstly, the 1’s complement of bit B1 obtained using an inverter and a 1 (Cin) are added to obtain the 2’s complement of the bit B1. Then, this 2’s complemented B1 is further added to A1. This will produce first bit of the output difference designated by S1, and a carry bit C1 which is connected to the input carry of the FA2.
Step 2 - 全加器 FA2 使用输入进位位 C1 与其输入位 A2 和输入位 B2 的 2 的补码相加，以产生第二个差位 (S2) 和进位位 C2。
Step 2 − The full adder FA2 uses the input carry bit C1 to add with its input bit A2 and the 2’s complement of the input bit B2 to produce the second difference bit (S2) and the carry bit C2.
Step 3 - 全加器 FA3 使用输入进位位 C2 与其输入位 A3 和输入位 B3 的 2 的补码相加，以产生第三个差位 (S3) 和进位位 C3。
Step 3 − The full adder FA3 uses the input carry bit C2 to add with its input bit A3 and the 2’s complement of the input bit B3 to produce the third difference bit (S3) and the carry bit C3.
Step 4 - 最后，全加器 FA4 使用进位位 C3 与其输入位 A4 和输入位 B4 的 2 的补码相加，以产生最后一个差位 (S4) 和最后一个进位位 C4。
Step 4 − Finally, the full adder FA4 uses the carry bit C3 to add with its input bit A4 and the 2’s complement of the input bit B4 to produce the last difference bit (S4) and last carry bit C4.
一旦产生所有结果位，它们就会被表示出来，给出两个二进制数的差为 S4S3S2S1 和借位 C4。
Once all the result bits are produced, they are expressed to give the difference of the two binary numbers as S4S3S2S1 and borrow bit C4.
Conclusion
这就是数字电子设备中的并行加法器和并行减法器的全部内容。并行加法器和减法器的最显着优势在于，与串行加法器和减法器相比，它们执行两个二进制数的算术加法和减法速度更快。
This is all about parallel adder and parallel subtractor in digital electronics. The most significant advantage of the parallel adder and subtractor is that they perform the arithmetic addition and subtraction of two binary numbers faster as compared to the serial adder and subtractor.