Embedded Systems 简明教程

Embedded Systems - Architecture Types

8051 微控制器使用 8 位数据总线工作。所以它们最多能支持 64K 外部数据内存和 64k 外部程序内存。总的来说，8051 微控制器可寻址 128k 外部内存。

The 8051 microcontrollers work with 8-bit data bus. So they can support external data memory up to 64K and external program memory of 64k at best. Collectively, 8051 microcontrollers can address 128k of external memory.

当数据和代码位于不同的存储器块中时，那么架构被称为 Harvard architecture 。当数据和代码位于同一个存储器块中时，那么架构被称为 Von Neumann architecture 。

When data and code lie in different memory blocks, then the architecture is referred as Harvard architecture. In case data and code lie in the same memory block, then the architecture is referred as Von Neumann architecture.

Von Neumann Architecture

冯·诺伊曼架构最早由计算机科学家约翰·冯·诺依曼提出。在该架构中，一条数据路径或总线既负责指令又负责数据。结果，CPU 一次只能执行一项操作。它要么从内存中获取一条指令，要么对数据执行读/写操作。因此，指令获取和数据操作不能同时进行，同时共享一条公共总线。

The Von Neumann architecture was first proposed by a computer scientist John von Neumann. In this architecture, one data path or bus exists for both instruction and data. As a result, the CPU does one operation at a time. It either fetches an instruction from memory, or performs read/write operation on data. So an instruction fetch and a data operation cannot occur simultaneously, sharing a common bus.

von neuman architecture

冯·诺伊曼架构支持简单的硬件。它允许使用一个单一顺序存储器。当今的处理速度远远超过内存访问时间，并且我们采用了一种非常快速但容量较小的存储器（高速缓存），它位于处理器的本地。

Von-Neumann architecture supports simple hardware. It allows the use of a single, sequential memory. Today’s processing speeds vastly outpace memory access times, and we employ a very fast but small amount of memory (cache) local to the processor.

Harvard Architecture

哈佛架构为指令和数据提供单独的存储和信号总线。该架构的数据存储完全包含在 CPU 中，并且无法将指令存储作为数据进行访问。使用内部数据总线，计算机为程序指令和数据分别设置存储器区域，从而允许同时访问指令和数据。

The Harvard architecture offers separate storage and signal buses for instructions and data. This architecture has data storage entirely contained within the CPU, and there is no access to the instruction storage as data. Computers have separate memory areas for program instructions and data using internal data buses, allowing simultaneous access to both instructions and data.

程序需要由操作员加载；处理器无法自行启动。在哈佛架构中，无需让这两个存储器共享属性。

Programs needed to be loaded by an operator; the processor could not boot itself. In a Harvard architecture, there is no need to make the two memories share properties.

harvard architecture

Von-Neumann Architecture vs Harvard Architecture

以下几点将冯·诺伊曼架构与哈佛架构区分开来。

The following points distinguish the Von Neumann Architecture from the Harvard Architecture.

Von-Neumann Architecture

Harvard Architecture

Single memory to be shared by both code and data.

Separate memories for code and data.

Processor needs to fetch code in a separate clock cycle and data in another clock cycle. So it requires two clock cycles.

Single clock cycle is sufficient, as separate buses are used to access code and data.

Higher speed, thus less time consuming.

Slower in speed, thus more time-consuming.

Simple in design.

Complex in design.

CISC and RISC

CISC 是一种复杂指令集计算机。它是一台可以寻址大量指令的计算机。

CISC is a Complex Instruction Set Computer. It is a computer that can address a large number of instructions.

在 20 世纪 80 年代初，计算机设计师建议计算机应该使用更少指令和简单的结构，以便它们可以在 CPU 内更快地执行而无需使用内存。此类计算机被归类为精简指令集计算机或 RISC。

In the early 1980s, computer designers recommended that computers should use fewer instructions with simple constructs so that they can be executed much faster within the CPU without having to use memory. Such computers are classified as Reduced Instruction Set Computer or RISC.

CISC vs RISC

以下几点将 CISC 与 RISC 区分开来 −

The following points differentiate a CISC from a RISC −

CISC

RISC

Larger set of instructions. Easy to program

Smaller set of Instructions. Difficult to program.

Simpler design of compiler, considering larger set of instructions.

Complex design of compiler.

Many addressing modes causing complex instruction formats.

Few addressing modes, fix instruction format.

Instruction length is variable.

Instruction length varies.

Higher clock cycles per second.

Low clock cycle per second.

Emphasis is on hardware.

Emphasis is on software.

Control unit implements large instruction set using micro-program unit.

Each instruction is to be executed by hardware.

Slower execution, as instructions are to be read from memory and decoded by the decoder unit.

Faster execution, as each instruction is to be executed by hardware.

Pipelining is not possible.

Pipelining of instructions is possible, considering single clock cycle.