Embedded Systems 简明教程

Embedded Systems - Interrupts

中断是由硬件或软件发出的信号，指示需要立即注意的事件。每当中断发生时，控制器都会完成执行当前指令，并开始执行一个 Interrupt Service Routine (ISR) 或 Interrupt Handler 。ISR 会告诉处理器或控制器在中断发生时做什么。中断可以是硬件中断或软件中断。

An interrupt is a signal to the processor emitted by hardware or software indicating an event that needs immediate attention. Whenever an interrupt occurs, the controller completes the execution of the current instruction and starts the execution of an Interrupt Service Routine (ISR) or Interrupt Handler. ISR tells the processor or controller what to do when the interrupt occurs. The interrupts can be either hardware interrupts or software interrupts.

Hardware Interrupt

硬件中断是从外部设备（如磁盘控制器或外部外围设备）发送到处理器的电子警报信号。例如，当我们在键盘上按一个键或移动鼠标时，它们会触发硬件中断，导致处理器读取击键或鼠标位置。

A hardware interrupt is an electronic alerting signal sent to the processor from an external device, like a disk controller or an external peripheral. For example, when we press a key on the keyboard or move the mouse, they trigger hardware interrupts which cause the processor to read the keystroke or mouse position.

Software Interrupt

软件中断是由特殊情况或指令集中的特殊指令引起的，当它们被处理器执行时会引起中断。例如，如果处理器的算术逻辑单元运行一个将数字除以零的命令，从而导致除以零异常，从而导致计算机放弃计算或显示错误消息。软件中断指令的工作方式类似于子例程调用。

A software interrupt is caused either by an exceptional condition or a special instruction in the instruction set which causes an interrupt when it is executed by the processor. For example, if the processor’s arithmetic logic unit runs a command to divide a number by zero, to cause a divide-by-zero exception, thus causing the computer to abandon the calculation or display an error message. Software interrupt instructions work similar to subroutine calls.

What is Polling?

持续监视的状态被称为 polling 。微控制器持续检查其他设备的状态；在执行此操作时，它不执行任何其他操作，并消耗所有处理时间来进行监视。可以通过使用中断来解决此问题。

The state of continuous monitoring is known as polling. The microcontroller keeps checking the status of other devices; and while doing so, it does no other operation and consumes all its processing time for monitoring. This problem can be addressed by using interrupts.

在中断方法中，控制器仅在发生中断时响应。因此，不需要控制器定期监视接口和内置设备的状态（标志、信号等）。

In the interrupt method, the controller responds only when an interruption occurs. Thus, the controller is not required to regularly monitor the status (flags, signals etc.) of interfaced and inbuilt devices.

Interrupts v/s Polling

以下是将中断与轮询区别开来的类比 −

Here is an analogy that differentiates an interrupt from polling −

Interrupt

Polling

An interrupt is like a shopkeeper. If one needs a service or product, he goes to him and apprises him of his needs. In case of interrupts, when the flags or signals are received, they notify the controller that they need to be serviced.

The polling method is like a salesperson. The salesman goes from door to door while requesting to buy a product or service. Similarly, the controller keeps monitoring the flags or signals one by one for all devices and provides service to whichever component that needs its service.

Interrupt Service Routine

对于每个中断，都必须有一个中断服务例程 (ISR) 或 interrupt handler 。当发生中断时，微控制器会运行中断服务例程。对于每个中断，内存中都有一个固定位置，用于保存其中断服务例程 ISR 的地址。为保存 ISR 地址而留出的内存位置表称为中断向量表。

For every interrupt, there must be an interrupt service routine (ISR), or interrupt handler. When an interrupt occurs, the microcontroller runs the interrupt service routine. For every interrupt, there is a fixed location in memory that holds the address of its interrupt service routine, ISR. The table of memory locations set aside to hold the addresses of ISRs is called as the Interrupt Vector Table.

Interrupt Vector Table

在 8051 中，包括 RESET 在内有六个中断。

There are six interrupts including RESET in 8051.

Interrupts

ROM Location (Hex)

Interrupts

ROM Location (HEX)

Serial COM (RI and TI)

0023

Timer 1 interrupts(TF1)

001B

External HW interrupt 1 (INT1)

0013

P3.3 (13)

External HW interrupt 0 (INT0)

0003

P3.2 (12)

Timer 0 (TF0)

000B

Reset

0000

When the reset pin is activated, the 8051 jumps to the address location 0000. This is power-up reset.
Two interrupts are set aside for the timers: one for timer 0 and one for timer 1. Memory locations are 000BH and 001BH respectively in the interrupt vector table.
Two interrupts are set aside for hardware external interrupts. Pin no. 12 and Pin no. 13 in Port 3 are for the external hardware interrupts INT0 and INT1, respectively. Memory locations are 0003H and 0013H respectively in the interrupt vector table.
Serial communication has a single interrupt that belongs to both receive and transmit. Memory location 0023H belongs to this interrupt.

Steps to Execute an Interrupt

当一个中断变得活跃时，微控制器将经历以下步骤 −

When an interrupt gets active, the microcontroller goes through the following steps −

The microcontroller closes the currently executing instruction and saves the address of the next instruction (PC) on the stack.
It also saves the current status of all the interrupts internally (i.e., not on the stack).
It jumps to the memory location of the interrupt vector table that holds the address of the interrupts service routine.
The microcontroller gets the address of the ISR from the interrupt vector table and jumps to it. It starts to execute the interrupt service subroutine, which is RETI (return from interrupt).
Upon executing the RETI instruction, the microcontroller returns to the location where it was interrupted. First, it gets the program counter (PC) address from the stack by popping the top bytes of the stack into the PC. Then, it start to execute from that address.

Edge Triggering vs. Level Triggering

中断模块有两种类型——电平触发或边沿触发。

Interrupt modules are of two types − level-triggered or edge-triggered.

Level Triggered

Edge Triggered

A level-triggered interrupt module always generates an interrupt whenever the level of the interrupt source is asserted.

An edge-triggered interrupt module generates an interrupt only when it detects an asserting edge of the interrupt source. The edge gets detected when the interrupt source level actually changes. It can also be detected by periodic sampling and detecting an asserted level when the previous sample was de-asserted.

If the interrupt source is still asserted when the firmware interrupt handler handles the interrupt, the interrupt module will regenerate the interrupt, causing the interrupt handler to be invoked again.

Edge-triggered interrupt modules can be acted immediately, no matter how the interrupt source behaves.

Level-triggered interrupts are cumbersome for firmware.

Edge-triggered interrupts keep the firmware’s code complexity low, reduce the number of conditions for firmware, and provide more flexibility when interrupts are handled.

Enabling and Disabling an Interrupt

复位后，即使所有中断都被激活，所有中断也会被禁用。必须使用软件启用中断，以便微控制器响应这些中断。

Upon Reset, all the interrupts are disabled even if they are activated. The interrupts must be enabled using software in order for the microcontroller to respond to those interrupts.

IE（中断使能）寄存器负责启用和禁用中断。IE 是一个可寻址寄存器。

IE (interrupt enable) register is responsible for enabling and disabling the interrupt. IE is a bitaddressable register.

Interrupt Enable Register

ET2

ET1

EX1

ET0

EX0

EA − Global enable/disable.
- − Undefined.
ET2 − Enable Timer 2 interrupt.
ES − Enable Serial port interrupt.
ET1 − Enable Timer 1 interrupt.
EX1 − Enable External 1 interrupt.
ET0 − Enable Timer 0 interrupt.
EX0 − Enable External 0 interrupt.

要启用中断，我们会执行以下步骤 −

To enable an interrupt, we take the following steps −

Bit D7 of the IE register (EA) must be high to allow the rest of register to take effect.
If EA = 1, interrupts will be enabled and will be responded to, if their corresponding bits in IE are high. If EA = 0, no interrupts will respond, even if their associated pins in the IE register are high.

Interrupt Priority in 8051

我们可以通过向任何一个中断分配更高优先级来更改中断优先级。这由对名为 IP (中断优先级) 的寄存器进行编程来完成。

We can alter the interrupt priority by assigning the higher priority to any one of the interrupts. This is accomplished by programming a register called IP (interrupt priority).

下图显示了 IP 寄存器的位。在复位后，IP 寄存器包含所有 0。要向任何一个中断提供更高的优先级，我们会让 IP 寄存器中对应的位变为高电平。

The following figure shows the bits of IP register. Upon reset, the IP register contains all 0’s. To give a higher priority to any of the interrupts, we make the corresponding bit in the IP register high.

PT1

PX1

PT0

PX0

IP.7

Not Implemented.

IP.6

Not Implemented.

IP.5

Not Implemented.

IP.4

Not Implemented.

PT1

IP.3

Defines the Timer 1 interrupt priority level.

PX1

IP.2

Defines the External Interrupt 1 priority level.

PT0

IP.1

Defines the Timer 0 interrupt priority level.

PX0

IP.0

Defines the External Interrupt 0 priority level.

Interrupt inside Interrupt

如果 8051 正在执行属于中断的 ISR，而另一个中断变得活跃，会发生什么？在这种情况下，高优先级中断可以中断低优先级中断。这称为 interrupt inside interrupt 。在 8051 中，低优先级中断可以被高优先级中断中断，但不能被任何另一个低优先级中断中断。

What happens if the 8051 is executing an ISR that belongs to an interrupt and another one gets active? In such cases, a high-priority interrupt can interrupt a low-priority interrupt. This is known as interrupt inside interrupt. In 8051, a low-priority interrupt can be interrupted by a high-priority interrupt, but not by any another low-priority interrupt.

Triggering an Interrupt by Software

有时我们需要通过模拟的方式测试 ISR。这可以使用向中断设置高电平的简单指令来完成，从而导致 8051 跳至中断向量表。例如，为定时器 1 将 IE 位设置为 1。指令 SETB TF1 会中断 8051 正在进行的任何操作，并强制它跳至中断向量表。

There are times when we need to test an ISR by way of simulation. This can be done with the simple instructions to set the interrupt high and thereby cause the 8051 to jump to the interrupt vector table. For example, set the IE bit as 1 for timer 1. An instruction SETB TF1 will interrupt the 8051 in whatever it is doing and force it to jump to the interrupt vector table.