Makefile 简明教程

Defining Rules in Makefile

现在我们将学习 Makefile 的规则。

We will now learn the rules for Makefile.

Makefile 目标规则的一般语法为：

The general syntax of a Makefile target rule is −

target [target...] : [dependent ....]
[ command ...]

在以上代码中，括号中的参数是可选的，省略号表示一个或多个。此处，请注意，每个命令前缀的制表符是必需的。

In the above code, the arguments in brackets are optional and ellipsis means one or more. Here, note that the tab to preface each command is required.

下面给出了一个简单的示例，其中您定义了一个规则，以便从另外三个文件制作目标 hello。

A simple example is given below where you define a rule to make your target hello from three other files.

hello: main.o factorial.o hello.o
   $(CC) main.o factorial.o hello.o -o hello

NOTE - 在此示例中，您必须提供从源文件制作所有目标文件的规则。

NOTE − In this example, you would have to give rules to make all object files from the source files.

语义非常简单。当您说“make target”时， make 查找适用的目标规则；并且，如果任何依赖项比目标新， make 会一次执行命令（在宏替换之后）。如果任何依赖项必须先制作，那么先发生这种情况（所以您有了递归）。

The semantics is very simple. When you say "make target", the make finds the target rule that applies; and, if any of the dependents are newer than the target, make executes the commands one at a time (after macro substitution). If any dependents have to be made, that happens first (so you have a recursion).

如果任何命令返回失败状态， Make 将终止。在这种情况下将显示以下规则：

Make terminates if any command returns a failure status. The following rule will be shown in such case −

clean:
   -rm *.o *~ core paper

Make 忽略以破折号开头的命令行上的返回状态。例如，谁会在乎没有核心文件？

Make ignores the returned status on command lines that begin with a dash. For example, who cares if there is no core file?

Make 在宏替换后会反映命令，向你展示正在发生什么。有时你可能想要关闭它。例如：

Make echoes the commands, after macro substitution to show you what is happening. Sometimes you might want to turn that off. For example −

install:
   @echo You must be root to install

人们预计 Makefile 中存在某些目标。你应该首先浏览。然而，合理解释就是所有目标（或仅仅是 make）、install 和 clean 都被找到了。

People have come to expect certain targets in Makefiles. You should always browse first. However, it is reasonable to expect that the targets all (or just make), install, and clean is found.

make all − It compiles everything so that you can do local testing before installing applications.
make install − It installs applications at right places.
make clean − It cleans applications, gets rid of the executables, any temporary files, object files, etc.

Makefile Implicit Rules

该命令是应该在我们使用源代码 x.cpp 构建可执行文件 x 时所有情况下都能起作用的命令。这可以表述为一个隐式规则：

The command is one that ought to work in all cases where we build an executable x out of the source code x.cpp. This can be stated as an implicit rule −

.cpp:
   $(CC) $(CFLAGS) $@.cpp $(LDFLAGS) -o $@

此隐式规则说明如何使用 x.c 来制作 x——在 x.c 上运行 cc 并将输出称为 x。这条规则是隐式的，因为没有提及具体目标。它可以在所有情况下使用。

This implicit rule says how to make x out of x.c — run cc on x.c and call the output x. The rule is implicit because no particular target is mentioned. It can be used in all cases.

另一个常见的隐式规则是根据 .cpp（源文件）构造 .o（对象）文件。

Another common implicit rule is for the construction of .o (object) files out of .cpp (source files).

.cpp.o:
   $(CC) $(CFLAGS) -c $<

alternatively

.cpp.o:
   $(CC) $(CFLAGS) -c $*.cpp