Digital-electronics 简明教程
Digital Electronics - Flip-Flops
触发器是一种顺序数字电子电路，具有两个稳定状态，可用于存储一位二进制数据。触发器是所有存储器设备的基本组成部分。
A flip-flop is a sequential digital electronic circuit having two stable states that can be used to store one bit of binary data. Flip-flops are the fundamental building blocks of all memory devices.
S-R Flip-Flop
这是最简单的触发器电路。它有一个设置输入 (S) 和一个复位输入 ®。当此电路中的 S 设置为活动时，输出 Q 将为高电平，而 Q' 将为低电平。如果 R 设置为活动，则输出 Q 为低电平，而 Q' 为高电平。一旦建立输出，电路的结果将保持不变，直到 S 或 R 发生变化，或者电源关闭。
This is the simplest flip-flop circuit. It has a set input (S) and a reset input ®. When in this circuit when S is set as active, the output Q would be high and the Q' will be low. If R is set to active then the output Q is low and the Q' is high. Once the outputs are established, the results of the circuit are maintained until S or R get changed, or the power is turned off.
J-K Flip-Flop
由于 SR 触发器中 S=R=1 对应的无效状态，因此需要另一种触发器。JK 触发器仅使用正或负时钟转换器工作。JK 触发器的操作类似于 SR 触发器。当输入 J 和 K 不同时，输出 Q 在下一个时钟沿采用 J 的值。
Because of the invalid state corresponding to S=R=1 in the SR flip-flop, there is a need of another flip-flop. The JK flip-flop operates with only positive or negative clock transitions. The operation of the JK flip-flop is similar to the SR flip-flop. When the input J and K are different then the output Q takes the value of J at the next clock edge.
当 J 和 K 都为低电平时，输出将不发生变化。如果 J 和 K 都为高电平时，则在时钟沿，输出将从一个状态切换到另一个状态。
When J and K both are low then NO change occurs at the output. If both J and K are high, then at the clock edge, the output will toggle from one state to the other.
Truth Table of JK Flip-Flop
J |
K |
Q |
State |
0 |
0 |
0 |
No Change |
0 |
1 |
0 |
Reset |
1 |
0 |
1 |
Set |
1 |
1 |
Toggles |
Toggle |
J |
K |
Q(t) |
Q(t+1) |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
0 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
\mathrm{Q(t \: + \: 1) \: = \: j \: k \: Q(t)' \: + \: K’Q(t)}
\mathrm{Q(t \: + \: 1) \: = \: j \: k \: Q(t)' \: + \: K’Q(t)}
D Flip-Flop
在 D 触发器中，输出只能在正或负时钟转换时更改，并且当输入在其他时间更改时，输出将保持不受影响。D 触发器通常用于移位寄存器和计数器。D 触发器输出状态的变化取决于时钟的活动转换。输出 (Q) 与输入相同，并且仅在时钟的活动转换时发生变化。
In a D flip-flop, the output can only be changed at positive or negative clock transitions, and when the inputs changed at other times, the output will remain unaffected. The D flip-flops are generally used for shift-registers and counters. The change in output state of D flip-flop depends upon the active transition of clock. The output (Q) is same as input and changes only at active transition of clock
T Flip-Flop
T 触发器（触发器切换）是 JK 触发器的简化版本。T 触发器是通过将 J 和 K 输入连接在一起而获得的。该触发器有一个输入端和时钟输入。这些触发器被称为 T 触发器，因为它们能够切换输入状态。触发器切换主要用于计数器。
A T flip-flop (Toggle Flip-flop) is a simplified version of JK flip-flop. The T flop is obtained by connecting the J and K inputs together. The flip-flop has one input terminal and clock input. These flip-flops are said to be T flip-flops because of their ability to toggle the input state. Toggle flip-flops are mostly used in counters.
