Digital-electronics 简明教程

Implementation of NAND/NOR gate using CMOS

在数字电子学中， NAND 和 NOR 门是两个通用逻辑门，用于对多个输入变量执行布尔运算。这些门根据所施加输入的组合产生输出。

In digital electronics, NAND and NOR gates are two universal logic gates that are used to perform Boolean operations on multiple input variables. These gates produce an output based on the combination of inputs applied.

NAND 门和 NOR 门用作数字电路和系统中的基本构建模块。我们可以在 DTL、RTL、TTL 和 CMOS 等不同技术中设计和实现 NAND 门和 NOR 门。本章讨论了使用 CMOS 技术实现 NAND 门和 NOR 门。

NAND and NOR gates are used as the fundamental building blocks in the digital circuits and systems. We can design and implement the NAND and NOR gates in different technologies such as DTL, RTL, TTL, and CMOS. This chapter deals with implementation of NAND and NOR gates using CMOS technology.

在 CMOS（互补金属氧化物半导体）技术中，NAND 和 NOR 逻辑门是通过串联和并联连接 NMOS 和 PMOS 晶体管来设计的。CMOS 技术中双输入逻辑门的框图如下图所示。

In CMOS (Complementary Metal Oxide Semiconductor) technology, the NAND and NOR logic gates are designed by connecting NMOS and PMOS transistors in series and parallel connections. The block diagram of a 2-input logic gate in CMOS technology is shown in the following figure.

在使用 CMOS 技术深入了解 NAND 和 NOR 门之前，让我们首先单独研究 NAND 和 NOR 门的基本原理。

Before getting deeper into the NAND and NOR gate using CMOS technology. Let’s first study the basics of NAND and NOR gates individually.

NAND Gate

NAND 门是 NOT 门和 AND 门的组合，其中一个 NOT 门连接到 AND 门的输出端。因此，它也被称为反相 AND 门。

The NAND gate is a combination of NOT gate and AND gate, where a NOT gate connected to the output of the AND gate. Thus, it is also known as NOTed AND gate.

\mathrm{AND \: 门 \: + \: NOT \: 门 \: = \: NAND \: 门}

\mathrm{AND \: Gate \: + \: NOT \: Gate \: = \: NAND \: Gate}

双输入 NAND 门的逻辑电路符号如下图所示 −

The logic circuit symbol of a two input NAND gate is shown in the following figure −

implementation of nand nor gate using cmos 1

当应用于 NAND 门的所有输入都为高电平或逻辑 1 时，NAND 门产生低电平或逻辑 0 输出。对于所有其他输入组合，它产生高电平或逻辑 1 输出。

The NAND gate produces a low or logic 0 output when all inputs applied to it are high or logic 1. For all other input combinations, it produces a high or logic 1 output.

Truth Table of NAND Gate

truth table of a two input NAND gate 如下所示 −

The truth table of a two input NAND gate is shown here −

Inputs	Output
A	B
Y	0
0	1
0	1
1	1
0	1
1	1

从这个真值表中，我们可以写出 NAND 门的布尔表达式，如下所示。

From this truth table, we can write the Boolean expression of the NAND gate, as follows.

\mathrm{Y \: = \: \overline{A\cdot B}}

这里，Y 是输出变量，A 和 B 是输入变量。

Here, Y is the output variable, and A and B are the input variables.

NOR Gate

NOR 门是数字电子设备中的一个通用逻辑门。它是两个基本逻辑门的组合，即 NOT 门和 OR 门，它是通过将 NOT 门连接到 OR 门的输出端而实现的。因此，

The NOR gate is a universal logic gate in digital electronics. It is a combination of two basic logic gates namely, NOT gate and OR gate, where it is realized by connecting a NOT gate to the output of the OR gate. Therefore,

\mathrm{OR \: 门 \: + \: NOT \: 门 \: = \: NOR \: 门}

\mathrm{OR \: Gate \: + \: NOT \: Gate \: = \: NOR \: Gate}

implementation of nand nor gate using cmos 2

当 NOR 门的所有输入都为低电平或逻辑 0 时，该 NOR 门的输出为高电平或逻辑 1。对于所有其他输入组合，NOR 门的输出为低电平或逻辑 0。

The output of the NOR gate is high or logic 1, when all its inputs are low or logic 0. For all other input combinations, the output of the NOR gate is low or logic 0.

Truth Table of NOR Gate

以下为 truth table of a two input NOR gate 描述了它的操作 −

The following is the truth table of a two input NOR gate that describing its operation −

Inputs	Output
A	B
Y	0
0	1
0	1
0	1
0	0
1	1

从这个真值表中，我们可以写出 NOR 门的布尔表达式，如下所示。

From this truth table, we can write the Boolean expression of the NOR gate, as follows.

\mathrm{Y \: = \: \overline{A \: + \: B}}

这里，Y 是输出变量，A 和 B 是输入变量。

Here, Y is the output variable, and A and B are the input variables.

上述内容就是有关 NAND 门和 NOR 门的基本原理。现在，我们来讨论使用 CMOS 技术实现 NAND 门和 NOR 门的方法。

This is all about the basics of NAND and NOR gate. Let us now discuss the implementation of NAND and NOR gates using CMOS technology.

NAND Gate Using CMOS Technology

可以通过使用 PMOS 和 NMOS 晶体管在 CMOS 技术中实现 NAND 门。以 CMOS 技术构建的双输入 NAND 门的电路图如下图所示 −

The NAND gate can be implemented in CMOS technology by using PMOS and NMOS transistors. The circuit diagram of a two input NAND gate in CMOS technology is shown in the following figure −

implementation of nand nor gate using cmos 3

它由两个 PMOS 晶体管 Q1 和 Q2 以及两个 NMOS 晶体管 Q3 和 Q4 组成。PMOS 晶体管并联连接在电源 VDD 与输出端 Y 之间。类似地，NMOS 晶体管串联连接在输出端 Y 和接地端 GND 之间。

It consists of two PMOS transistors Q1 and Q2 and two NMOS transistors Q3 and Q4. The PMOS transistors are connected in parallel between the power supply VDD and the output terminal Y. Similarly, the NMOS transistors are connected in series between the output terminal Y and the ground terminal GND.

现在，让我们来了解该 CMOS NAND 门的操作原理。

Now, let us understand the operation of this CMOS NAND gate.

Case 1: When Input A is Low and Input B is Low

在这种情况下，当输入 A 和 B 都为低电平时，PMOS 晶体管 Q1 和 Q2 为导通状态，NMOS 晶体管 Q3 和 Q4 为截止状态。因此，在电源电压 VDD 和输出端 Y 之间存在一条闭合通路。

In this case, when both inputs A and B are low, the PMOS transistors Q1 and Q2 are ON and the NMOS transistors Q3 and Q4 are OFF. Hence, there is a closed path between the supply voltage VDD and the output terminal Y.

因此，输出 Y 将连接到电压等级 VDD。而且，由于两个 NMOS 晶体管都是关，因此输出终端和接地终端之间不存在通路。在这种条件下，输出线将保持电压等级为 VDD，这表示输出高电平。

Thus, the output Y will be connected to the voltage level VDD. Also, there is no path between the output terminal and the ground terminal as both NMOS transistors are OFF. Under this condition, the output line will maintain the voltage level at VDD, which indicates the output High.

Thus, when A = 0 and B = 0, then Y = 1

Case 2: When Input A is Low and Input B is High

在这种情况下，PMOS 晶体管 Q1 将开，而 PMOS 晶体管 Q2 将关。NMOS 晶体管 Q3 将关，而 NMOS 晶体管 Q4 将开。

In this case, the PMOS transistor Q1 will be ON while the PMOS transistor Q2 will be OFF. The NMOS transistor Q3 will be OFF and the NMOS transistor Q4 will be ON.

对于 CMOS 晶体管的这种开关条件，电源 VDD 将通过 PMOS 晶体管 Q1 获得通往输出终端的通路。由于，NMOS 晶体管 Q3 和 Q4 串联连接，并且 NMOS 晶体管 Q3 关。因此，输出终端和接地终端之间没有通路。

For this switching condition of the CMOS transistors, the power supply VDD will get a path to the output terminal through the PMOS transistor Q1. Since, the NMOS transistor Q3 and Q4 are connected in series and the NMOS transistor Q3 is OFF. Hence, there is no path between the output terminal and the ground terminal.

因此，输出终端 Y 保持电压等级为 VDD，并导致高电平输出。

Therefore, the output terminal Y maintain the voltage level at VDD and results in a High output.

Thus, when A = 0 and B = 1, then Y = 1

Case 3: When Input A is High and Input B is Low

在这种情况下，PMOS 晶体管 Q1 将关，而 PMOS 晶体管 Q2 将开。NMOS 晶体管 Q3 将开，而 NMOS 晶体管 Q4 将关。

In this case, the PMOS transistor Q1 will be OFF and the PMOS transistor Q2 will be ON. The NMOS transistor Q3 will be ON and the NMOS transistor Q4 will be OFF.

对于 CMOS 晶体管的这种开关条件，输出终端将通过 PMOS 晶体管 Q2 连接到电源。由于，两个 NMOS 晶体管串联连接，并且 NMOS 晶体管 Q4 关。因此，输出终端和接地终端之间没有通路。

Under this switching condition of the CMOS transistors, the output terminal will connect to the power supply through the PMOS transistor Q2. Since, both NMOS transistors are connected in series and the NMOS transistor Q4 is OFF. Hence, there is no path between the output terminal and the ground terminal.

因此，输出线将保持电压等级为 VDD，并导致高电平输出。

Therefore, the output line will maintain the voltage level at VDD and results in a High output.

Thus, when A = 1 and B = 0, then Y = 1

Case 4: When Input A is High and Input B is High

在这种情况下，PMOS 晶体管 Q1 和 Q2 都将关，而 NMOS 晶体管都将开。在这种情况下，输出终端和电源 VDD 之间没有通路，但输出终端和接地终端之间有直接通路。这导致输出终端的接地电压等级并产生低电平输出。

In this case, both PMOS transistors Q1 and Q2 will be OFF and both NMOS transistors will be ON. In this case, there is no path between the output terminal and the power supply VDD, but there is a direct path between the output terminal and the ground terminal. This results in a ground voltage level at the output terminal and produces a Low output.

Hence, when A = 1 and B = 1, then Y = 0

此 CMOS NAND 门的操作在以下真值表中显示 −

The operation of this CMOS NAND gate is shown in the following truth table −

Inputs

Output

Low (0)

High (1)

Low (0)

High (1)

Low (0)

High (1)

这就是有关使用 CMOS 技术实现 NAND 门及其在不同输入组合下的操作的所有内容。

This is all about NAND gate implementation using CMOS technology and its operation for different input combinations.

现在让我们讨论使用 CMOS 技术实现和操作 NOR 门。

Let us now discuss the implementation and operation of NOR gate using CMOS technology.

NOR Gate Using CMOS Technology

与 CMOS NAND 门类似，我们还可以使用 PMOS 和 NMOS 晶体管设计 NOR 门。使用 CMOS 技术的两输入 NOR 门电路图如下图所示 −

Similar to CMOS NAND gate, we can also design a NOR gate using PMOS and NMOS transistors. The circuit diagram of a two input NOR gate using CMOS technology is shown in the following figure −

implementation of nand nor gate using cmos 4

此 CMOS NOR 门是使用两个 PMOS 晶体管 Q1 和 Q2 以及两个 NMOS 晶体管 Q3 和 Q4 设计的。其中 PMOS 晶体管串联连接在电源电压 VDD 和输出终端 Y 之间。NMOS 晶体管并联连接在输出终端 Y 和接地终端 GND 之间。

This CMOS NOR gate is designed by using two PMOS transistors Q1 and Q2 and two NMOS transistor Q3 and Q4. Where the PMOS transistors are connected in series between the supply voltage VDD and the output terminal Y. The NMOS transistors are connected in parallel between the output terminal Y and the ground terminal GND.

现在，让我们了解此 CMOS 电路如何作为两输入 NOR 门操作。

Now, let us understand how does this CMOS circuit operate as a two input NOR gate.

Case 1: When Input A is Low and Input B is Low

在这种情况下，PMOS 晶体管 Q1 和 Q2 都将开，而 NMOS 晶体管 Q3 和 Q4 都将关。

In this case, both PMOS transistors Q1 and Q2 will be ON and both NMOS transistors Q3 and Q4 will be OFF.

在 CMOS 晶体管的这种转换条件下，通过导通的 PMOS 晶体管在电源电压 VDD 与输出端 Y 之间有一条路径。但在输出端 Y 与接地端 GND 之间没有路径。这使输出保持在电压电平 VDD 处，因此输出将为 High。

Under this switching condition of the CMOS transistors, there is a path between the supply voltage VDD and the output terminal Y through the ON PMOS transistors. But there is no path between the output terminal Y and the ground terminal GND. This maintains the output at the voltage level VDD and hence the output will be High.

Thus, when A = 0 and B = 0, then Y = 1

Case 2: When Input A is Low and Input B is High

在这种情况下，PMOS 晶体管 Q1 是导通的，PMOS 晶体管 Q2 是截止的，NMOS 晶体管 Q3 是截止的，而且 NMOS 晶体管 Q4 是导通的。

In this case, the PMOS transistor Q1 is ON, the PMOS transistor Q2 is OFF, the NMOS transistor Q3 is OFF, and the NMOS transistor Q4 is ON.

由于 PMOS 晶体管 Q1 和 Q2 串联连接，且晶体管 Q2 是截止的。因此，在电源 VDD 与输出端 Y 之间没有路径。但通过导通的 NMOS 晶体管 Q4，输出线 Y 与接地端 GND 之间有连接。这将输出端设置为接地电压，并使输出变为 Low。

Since, the PMOS transistors Q1 and Q2 are connected in series and the transistor Q2 is OFF. Thus, there is no path between the power supply VDD and the output terminal Y. But there is a connection between the output line Y and the ground terminal GND through the ON NMOS transistor Q4. This sets the output terminal to ground voltage and makes the output Low.

Therefore, when A = 0 and B = 1, then Y = 0

Case 3: When Input A is High and Input B is Low

在此条件下，PMOS 晶体管 Q1 是截止的，PMOS 晶体管 Q2 是导通的，NMOS 晶体管 Q3 是导通的，而且 NMOS 晶体管 Q4 是截止的。

In this condition, the PMOS transistor Q1 is OFF, the PMOS transistor Q2 is ON, the NMOS transistor Q3 is ON, and the NMOS transistor Q4 is OFF.

在这种情况下，由于 PMOS 晶体管 Q1 截止，在电源 VDD 与输出线 Y 之间没有闭合路径。但通过导通的 NMOS 晶体管 Q3，输出线 Y 与接地端 GND 之间有闭合路径。因此，输出端连接至接地电位，并使输出变为 Low。

In this case, there is no closed path between the power supply VDD and the output line Y due to OFF PMOS transistor Q1. But there is a closed between the output line Y and the ground terminal GND through the ON NMOS transistor Q3. Hence, the output terminal is connected to the ground potential and makes the output Low.

Thus, when A = 1 and B = 0, then Y = 0

Case 4 – When Input A is High and Input B is High

在这种情况下，PMOS 晶体管 Q1 和 Q2 均截止，且 NMOS 晶体管 Q3 和 Q4 均导通。在此条件下，在电源电压 VDD 与输出端 Y 之间没有路径。但在输出端 Y 与接地端 GND 之间有闭合路径。这使输出线保持在接地电压电平，因此输出将为 Low。

In this case, both PMOS transistors Q1 and Q2 are OFF and both NMOS transistors Q3 and Q4 are ON. Under this condition, there is no path between the supply voltage VDD and the output terminal Y. But there is a closed path between the output terminal Y and the ground terminal GND. This maintains the output line at ground voltage level and hence the output will be Low.

Thus, when A = 1 and B = 1, then Y = 0

CMOS NOR 门的这一完整操作可以概括为下文给出的真值表的形式。

This complete operation of the CMOS NOR gate can be summarized in the form of a truth table which is given below.

Inputs

Output

Low (0)

High (1)

Low (0)

High (1)

Low (0)

High (1)

Low (0)

High (1)

Advantages of NAND and NOR Gates using CMOS Technology

利用 CMOS 技术实现的 NAND 门和 NOR 门比其他技术提供了一些优点。CMOS NAND 门和 NOR 门的一些主要优点在此列出 −

NAND and NOR gates implemented in CMOS technology offer several benefits over other technologies. Some of the key advantages of CMOS NAND and NOR gates are listed here −

CMOS NAND and NOR gates consume relatively low power. This advantage makes these logic gates well-suited to use in battery powered devices.
NAND and NOR gates designed using CMOS technology have high immunity against noise and interference. They can be designed to have a wider range of operating voltage.
The CMOS technology offers high-density integration that allows for implementing a large number of NAND and NOR gates on a single chip. These gates provide symmetrical output characteristics that allow them to integrate with different types of digital circuits seamlessly.
CMOS technology is one of the well-established, mature, and cost-effective semiconductor manufacturing technology. Hence, the CMOS NAND and NOR gates are relatively easy to manufacture and cost effective.

Applications of CMOS NAND and NOR Gates

CMOS NAND 门和 NOR 门由于具有优点和多功能性，而被广泛用于以下应用中 −

The CMOS NAND and NOR gates are widely used in the following applications due to their benefits and versatility −

CMOS NAND and NOR gates are widely used in the logic circuit designs to perform logical operations.
In digital systems, the CMOS NAND and NOR gates are used to implement arithmetic circuits like adders, subtractors, multipliers, etc.
They are also used in memory units to implement memory cell structures.
CMOS NAND and NOR gates are also used to design multiplexers and demultiplexers.
Some other common applications of CMOS NAND and NOR gates include digital signal processing, digital timing circuits, analog to digital conversion, digital communication, etc.

Conclusion

CMOS NAND 和 NOR 门广泛应用于数字电子领域的各种应用中。这种类型的 NAND 和 NOR 门提供多种优势，例如高效率、低功耗、多功能性、低成本、高可靠性等。

The CMOS NAND and NOR gates are widely used in a variety of applications in the field of digital electronics. This type of NAND and NOR gates offer several advantages such as high efficiency, low power consumption, versatility, low cost, high reliability, etc.

在本章中，我们介绍了使用 CMOS 技术实现 NAND 和 NOR 门及其优势和应用。

In this chapter, we explained the implementation of NAND and NOR gates using CMOS technology along with their advantages and applications.