Digital-electronics 简明教程
Implementation of a Full Subtractor using Two Half Subtractors
减法器是一个组合逻辑电路，可以执行两个数字（或二进制数字）的减法并产生它们之间的差。它是一个组合逻辑电路。因此，减法器的输出仅取决于其当前输入。
A subtractor is a combinational logic circuit that can perform the subtraction of two numbers (or binary numbers) and produce the difference between them. It is a combinational logic circuit. Therefore, the output of the subtractor depends only on its present inputs.
减法器有两种类型，即，
There are two types of subtractors namely,
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Half Subtractor
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Full Subtractor
阅读本教程以了解如何使用半减法器实现全减法器。为了实现全减法器，我们需要两个半减法器。让我们从对半减法器和全减法器的简要概述开始。
Read this tutorial to find out how you can realize a full subtractor using half subtractors. For the implementation of a full subtractor, we require two half subtractors. Let’s start with a brief overview of half and full subtractors.
What is a Half Subtractor?
half-subtractor 是一个组合逻辑电路，它有两个输入和两个输出，其中一个输出是差位 (d)，另一个是借位 (b)。半减法器生成两个二进制位之间的差，并生成借位输出（如果有）。在减法 (A-B) 中，A 称为 Minuend ，B 称为 Subtrahend bit 。
A half-subtractor is a combinational logic circuit that has two inputs and two outputs where one output is difference bit (d) and another is the borrow bit (b). The half subtractor produces the difference between the two binary bits and also produces a borrow output (if any). In the subtraction (A-B), A is called Minuend and B is called Subtrahend bit.
半减法器的框图和逻辑电路图如图 1 所示。
The block diagram and logic circuit diagram of the half subtractor are shown in Figure-1.
从半减法器的逻辑图中可以看出，可以使用 XOR 门与非门和 AND 门来实现半减法器。
From the logic diagram of the half subtractor, it can be seen that a half subtractor can be realized using an XOR gate together with a NOT gate and an AND gate.
半减法器的差位 (d) 由 XORing 两个输入 A 和 B 得到。因此，
The difference bit (d) of the half subtractor is given by XORing the two inputs A and B. Therefore,
\mathbf{差值，\: d \: = \: A \oplus B \: = \: A’B \: + \: AB'}
\mathbf{Difference,\: d \: = \: A \oplus B \: = \: A’B \: + \: AB'}
半减法器的借位 (b) 是 A'（A 的补码）和 B 的 AND。因此，
The borrow (b) of the half subtractor is the AND of A' (compliment of A) and B. Therefore,
\mathbf{借用，\: b \: = \: A’B}
\mathbf{Borrow, \: b \: = \: A’B}
What is a Full Subtractor?
A full subtractor 也是一个组合逻辑电路，它有三个输入 A、B、bin 和两个输出“d”和“b”。其中，“A”是减数位，“B”是被减数位，“bin”是上一阶段产生的借位，“d”是输出差值位，而“b”是输出借位位。
A full subtractor is also a combinational logic circuit which has three inputs A, B, bin and two outputs "d" and "b". Where, "A" is the minuend bit, "B" is the subtrahend bit, "bin" is borrow produced at the previous stage, d is the output difference bit and b is the output borrow bit.
一个全减器的框图和电路图如图 2 所示。
The block diagram and circuit diagram of a full-subtractor is shown in Figure-2.
从全减器的逻辑图中，我们可以看到实现全减器需要两个异或门、两个非门、两个与门和一个或门。
From the logic diagram of the full subtractor, we can see that the implementation of a fullsubtractor requires two XOR gates, two NOT gates, two AND gates, and one OR gate.
现在，让我们讨论如何使用两个半减器实现全减器。
Now, let us discuss the realization of full subtractor using two half subtractors.
Implementation of a Full Subtractor using Two Half Subtractors
可以使用两个半减器来实现一个全减器。它将采用两个半减器和一个或门。使用两个半减器的全减器逻辑电路图如图 3 所示。
A full subtractor can be realized using two half subtractors. It will take two half-subtractors and one OR gate. The logic circuit diagram of the full subtractor using two half subtractors is shown in Figure-3.
第一个半减器对输入位 A 和 B 执行异或运算，然后对 A' 和 B 执行与运算以产生一个中间借位位。
The first half subtractor performs XOR operation on input bits A and B, and AND operation on A' and B to produce an intermediate borrow bit
第二个半减器对第一个异或门的输出和输入借位（bin）执行异或操作，第二个半电路线路的与门给出等于 (A’B + AB')'.bin 的输出。
The second half subtractor performs the XOR operation on the output of first XOR gate and the input borrow bit (bin), and the AND gate of the second half circuit gives an output equal to (A’B + AB')'.bin.
第二个异或门的输出是输出差位（d），而输出借位（b）是通过对两个与门的输出执行或运算获得的。
The output of the second XOR gate is the output different bit (d), and the output borrow bit (b) is obtained by ORing the outputs of two AND gates.
以这种方式，我们可以通过级联两个半减器来实现全减器，如上图所示。
In this way, we can realize a full subtractor by cascading two half subtractors, as shown in the above figure