Digital-electronics 简明教程
Implementation of OR Gate from NAND Gate
NAND 门是一个通用逻辑门，我们可以用它来实现任何逻辑门。阅读本教程了解如何使用 NAND 门实现或门。在进入实现部分之前，让我们简要概述一下或门和 NAND 门。
NAND Gate is a universal logic gate, using which we can realize any logic gate. Read this tutorial to find out how you can realize an OR gate using a NAND gate. Before going into the implementation part, let’s have a brief overview of OR and NAND gates.
What is an OR Gate?
{@s0} 是一个基本的逻辑门。或门可以接受两个或两个以上的输入，但仅给出单个输出。如果或门的任何一个输入处于高电平或逻辑 1 状态，则它会给出高电平（逻辑 1）输出，否则，它会给出低电平（逻辑 0）状态作为输出。因此，或门的输出只有在所有输入均为低电平或逻辑 0 状态时，才是低或逻辑 0 状态。
An OR Gate is a basic logic gate. An OR gate may accept two or more than two inputs, but gives only one output. The OR gate gives a HIGH (Logic 1) output if any one of its inputs is in the HIGH or Logic 1 state, otherwise, it gives a LOW (Logic 0) state as output. Therefore, the output of the OR gate is LOW or Logic 0 state, only if its all inputs are LOW or Logic 0 state.
或门又称为{@s1}或{@s2}。两个输入或门的逻辑符号如图 1 所示。
The OR gate is also known as an "any or all gate" or "an inclusive OR gate". The logic symbol of a two input OR gate is shown in Figure-1.
Output Equation of OR Gate
如果 A 和 B 是输入变量，Y 是输出变量，则或门的输出方程式由下式给出：
If A and B are the input variables and Y is the output variable, then the output equation of the OR gate is given by,
\mathrm{Y \: = \: A \: + \: B}
其中“+”符号表示或操作。它将 Y 解释为等于 A 或 B。
Where, the '+' symbol represents the OR operation. It is read as Y is equal to A OR B.
What is a NAND Gate?
NAND 门是一种通用逻辑门。通用逻辑门是可以用来实现任何类型的逻辑表达式或任何其它类型逻辑门的逻辑门。
The NAND Gate is a type of universal logic gate. Where, a universal logic gate is one that can be used to realize any kind logical expression or any other type of logic gate.
NAND 门实际上是两个基本逻辑门的组合，即 AND 门和 NOT 门，即，
A NAND gate is basically a combination of two basic logic gates namely AND gate and NOT gate, i.e.,
\mathrm{NAND \: Logic \: = \: AND \: Logic \: + \: NOT \: Logic}
NAND 门是一种当所有输入都是 HIGH 时输出为 LOW（逻辑 0），当任何一种输入为 LOW（逻辑 0）时输出为 HIGH（逻辑 1）的逻辑门。因此，NAND 门的操作与 AND 门相反。一个两个输入的 NAND 门的逻辑符号如图 2 所示。
A NAND gate is the type of logic gate whose output is LOW (Logic 0) when all its inputs are high, and its output is HIGH (Logic 1), when any of its inputs is LOW (Logic 0). Therefore, the operation of the NAND gate is opposite that of the AND gate. The logic symbol of a two input NAND gate is shown in Figure-2.
Output Equation of NAND Gate
如果 A 和 B 是一个 NAND 门的输入变量，Y 是输出变量，则其输出可表示为
If A and B are the input variables and Y is the output variable of the NAND gate, then its output is given by,
\mathrm{Y \: = \: \overline{A \: \cdot \: B} \: = \: (A \: \cdot \: B)'}
它被解释为“Y 等于 A 点 B 全整”。
It is read as "Y is equal to A.B whole bar".
Implementation of OR Gate from NAND Gate
NAND 门是一个万能门，因此可以用它来实现 OR 门。使用 NAND 门实现 OR 门如图 3 所示。
The NAND gate is a universal gate, therefore, it can be used to realize the OR gate. The implementation of OR gate using the NAND gate is shown in Figure-3.
图 3 所示的 NAND 电路等效于 OR 门。它也被称为冒泡 NAND 门，其中冒泡 NAND 门在操作上等效于 OR 门。
The NAND circuit shown in Figure-3 is equivalent to an OR gate. It is also known as bubbled NAND Gate, where the bubbled NAND gate is equivalent to the OR gate in operation.
Theory of OR Gate using NAND Gate
为了用 NAND 门实现 OR 门，我们首先对输入 A 和 B 求补。这是由图 3 中的 NAND 门 1 和 2 完成的。然后，将这些取反输入（即 A' 和 B'）应用于 NAND 门（NAND 门 3）。因此，我们得到，
To realize the OR gate using NAND gate, we first complement the inputs A and B. This is done by the NAND Gate 1 and 2 in the above Figure-3. Then, these complemented inputs, i.e. A' and B' are applied to a NAND Gate (NAND Gate 3). Thus, we get,
\mathrm{Y \: = \: \overline{\bar{A} \: \cdot \: \bar{B}}}
使用德·摩根定律，我们有，
Using De Morgen’s Law, we have,
\mathrm{Y \: = \: \bar{\bar{A}} \: + \: \bar{\bar{B}} \: = \: A \: + \: B}
这是 OR 门的输出方程。因此，图 3 中 NAND 门的逻辑电路等效于 OR 门。
This is the output equation of the OR gate. Therefore, the logic circuit of NAND gates in Figure-3 is equivalent to the OR Gate.